From patchwork Sat Sep 19 00:03:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Gang X-Patchwork-Id: 519612 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id F2212140789 for ; Sat, 19 Sep 2015 10:04:04 +1000 (AEST) Received: from localhost ([::1]:42596 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zd5dK-0002EY-UC for incoming@patchwork.ozlabs.org; Fri, 18 Sep 2015 20:04:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40646) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zd5d5-0001xQ-40 for qemu-devel@nongnu.org; Fri, 18 Sep 2015 20:03:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zd5d1-0000d3-Lg for qemu-devel@nongnu.org; Fri, 18 Sep 2015 20:03:47 -0400 Received: from smtpbg63.qq.com ([103.7.29.150]:37918) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zd5d0-0000ZQ-TO for qemu-devel@nongnu.org; Fri, 18 Sep 2015 20:03:43 -0400 X-QQ-mid: esmtp28t1442621009t720t20936 Received: from localhost.localdomain (unknown [223.72.67.117]) by esmtp4.qq.com (ESMTP) with id ; Sat, 19 Sep 2015 08:03:28 +0800 (CST) X-QQ-SSF: 01000000000000F0FG500F00002000H X-QQ-FEAT: 92FxZ2TPvncr3T1TBZU2pmGgULXKfKAIx8xMIG/h9vV9HeLmizMGgQW1p9gwn Qyn0HBR/ItwzG5g+4RmwNbaru/iWfJzpTdYfpmvW2e7twQYa+w02BovETMGPK17TEancoXj hGJ3oGwRFMu39CnCfdVKpXojKyfzyEwl9mGGmc3aax7PyW8k9z0x+4XHr9DqEJF4qFwGpdP do2xy/moI5L0xWld/YOorZKYXzzO6YoV63azeu0H0eNu3fTBxAASb X-QQ-GoodBg: 0 X-QQ-CSender: gang.chen.5i5j@qq.com From: gang.chen.5i5j@gmail.com To: peter.maydell@linaro.org, rth@twiddle.net Date: Sat, 19 Sep 2015 08:03:26 +0800 Message-Id: <1442621006-4231-1-git-send-email-gang.chen.5i5j@gmail.com> X-Mailer: git-send-email 1.9.3 X-QQ-SENDSIZE: 520 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x X-Received-From: 103.7.29.150 Cc: qemu-devel@nongnu.org, xili_gchen_5257@hotmail.com, Chen Gang Subject: [Qemu-devel] [PATCH] target-tilegx: Implement v*add and v*sub instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Chen Gang Only according to helper_v1shrs. Signed-off-by: Chen Gang --- target-tilegx/helper.h | 8 +++++ target-tilegx/simd_helper.c | 77 +++++++++++++++++++++++++++++++++++++++++++++ target-tilegx/translate.c | 26 +++++++++++++-- 3 files changed, 109 insertions(+), 2 deletions(-) diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h index 15093973..c366984 100644 --- a/target-tilegx/helper.h +++ b/target-tilegx/helper.h @@ -5,12 +5,20 @@ DEF_HELPER_FLAGS_1(pcnt, TCG_CALL_NO_RWG_SE, i64, i64) DEF_HELPER_FLAGS_1(revbits, TCG_CALL_NO_RWG_SE, i64, i64) DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) +DEF_HELPER_FLAGS_2(v1add, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v1shru, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v1shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(v1sub, TCG_CALL_NO_RWG_SE, i64, i64, i64) + +DEF_HELPER_FLAGS_2(v2add, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v2shl, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v2shru, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v2shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(v2sub, TCG_CALL_NO_RWG_SE, i64, i64, i64) + +DEF_HELPER_FLAGS_2(v4add, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v4shl, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v4shru, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v4shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(v4sub, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target-tilegx/simd_helper.c b/target-tilegx/simd_helper.c index 6546337..ec589fe 100644 --- a/target-tilegx/simd_helper.c +++ b/target-tilegx/simd_helper.c @@ -22,6 +22,83 @@ #include "qemu-common.h" #include "exec/helper-proto.h" +uint64_t helper_v1add(uint64_t a, uint64_t b) +{ + uint64_t r = 0; + int i; + + for (i = 0; i < 64; i += 8) { + int64_t ae = (int8_t)(a >> i); + int64_t be = (int8_t)(b >> i); + r |= ((ae + be) & 0xff) << i; + } + return r; +} + +uint64_t helper_v2add(uint64_t a, uint64_t b) +{ + uint64_t r = 0; + int i; + + for (i = 0; i < 64; i += 16) { + int64_t ae = (int16_t)(a >> i); + int64_t be = (int16_t)(b >> i); + r |= ((ae + be) & 0xffff) << i; + } + return r; +} + +uint64_t helper_v4add(uint64_t a, uint64_t b) +{ + uint64_t r = 0; + int i; + + for (i = 0; i < 64; i += 32) { + int64_t ae = (int32_t)(a >> i); + int64_t be = (int32_t)(b >> i); + r |= ((ae + be) & 0xffffffff) << i; + } + return r; +} + +uint64_t helper_v1sub(uint64_t a, uint64_t b) +{ + uint64_t r = 0; + int i; + + for (i = 0; i < 64; i += 8) { + int64_t ae = (int8_t)(a >> i); + int64_t be = (int8_t)(b >> i); + r |= ((ae - be) & 0xff) << i; + } + return r; +} + +uint64_t helper_v2sub(uint64_t a, uint64_t b) +{ + uint64_t r = 0; + int i; + + for (i = 0; i < 64; i += 16) { + int64_t ae = (int16_t)(a >> i); + int64_t be = (int16_t)(b >> i); + r |= ((ae - be) & 0xffff) << i; + } + return r; +} + +uint64_t helper_v4sub(uint64_t a, uint64_t b) +{ + uint64_t r = 0; + int i; + + for (i = 0; i < 64; i += 32) { + int64_t ae = (int32_t)(a >> i); + int64_t be = (int32_t)(b >> i); + r |= ((ae - be) & 0xffffffff) << i; + } + return r; +} uint64_t helper_v1shl(uint64_t a, uint64_t b) { diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index c8247ac..2246243 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -1024,8 +1024,12 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, break; case OE_RRR(V1ADDUC, 0, X0): case OE_RRR(V1ADDUC, 0, X1): + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; case OE_RRR(V1ADD, 0, X0): case OE_RRR(V1ADD, 0, X1): + gen_helper_v1add(tdest, tsrca, tsrcb); + mnemonic = "v1add"; + break; case OE_RRR(V1ADIFFU, 0, X0): case OE_RRR(V1AVGU, 0, X0): return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; @@ -1095,12 +1099,20 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, break; case OE_RRR(V1SUBUC, 0, X0): case OE_RRR(V1SUBUC, 0, X1): + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; case OE_RRR(V1SUB, 0, X0): case OE_RRR(V1SUB, 0, X1): + gen_helper_v1sub(tdest, tsrca, tsrcb); + mnemonic = "v1sub"; + break; case OE_RRR(V2ADDSC, 0, X0): case OE_RRR(V2ADDSC, 0, X1): + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; case OE_RRR(V2ADD, 0, X0): case OE_RRR(V2ADD, 0, X1): + gen_helper_v2add(tdest, tsrca, tsrcb); + mnemonic = "v2add"; + break; case OE_RRR(V2ADIFFS, 0, X0): case OE_RRR(V2AVGS, 0, X0): case OE_RRR(V2CMPEQ, 0, X0): @@ -1162,13 +1174,20 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, break; case OE_RRR(V2SUBSC, 0, X0): case OE_RRR(V2SUBSC, 0, X1): + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; case OE_RRR(V2SUB, 0, X0): case OE_RRR(V2SUB, 0, X1): + gen_helper_v2sub(tdest, tsrca, tsrcb); + mnemonic = "v2sub"; + break; case OE_RRR(V4ADDSC, 0, X0): case OE_RRR(V4ADDSC, 0, X1): + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; case OE_RRR(V4ADD, 0, X0): case OE_RRR(V4ADD, 0, X1): - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; + gen_helper_v4add(tdest, tsrca, tsrcb); + mnemonic = "v4add"; + break; case OE_RRR(V4INT_H, 0, X0): case OE_RRR(V4INT_H, 0, X1): tcg_gen_shri_tl(tdest, tsrcb, 32); @@ -1202,9 +1221,12 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, break; case OE_RRR(V4SUBSC, 0, X0): case OE_RRR(V4SUBSC, 0, X1): + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; case OE_RRR(V4SUB, 0, X0): case OE_RRR(V4SUB, 0, X1): - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; + gen_helper_v2sub(tdest, tsrca, tsrcb); + mnemonic = "v2sub"; + break; case OE_RRR(XOR, 0, X0): case OE_RRR(XOR, 0, X1): case OE_RRR(XOR, 5, Y0):