From patchwork Fri Sep 18 15:04:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Snow X-Patchwork-Id: 519433 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5D677140770 for ; Sat, 19 Sep 2015 02:04:33 +1000 (AEST) Received: from localhost ([::1]:40188 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zcy9H-00043H-Ao for incoming@patchwork.ozlabs.org; Fri, 18 Sep 2015 12:04:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34037) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zcy05-0004su-5p for qemu-devel@nongnu.org; Fri, 18 Sep 2015 11:55:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zcy01-0002jv-Ul for qemu-devel@nongnu.org; Fri, 18 Sep 2015 11:55:01 -0400 Received: from mx1.redhat.com ([209.132.183.28]:50470) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZcxDW-0001Dv-6Q for qemu-devel@nongnu.org; Fri, 18 Sep 2015 11:04:50 -0400 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (Postfix) with ESMTPS id CA969C0B2E14; Fri, 18 Sep 2015 15:04:49 +0000 (UTC) Received: from scv.usersys.redhat.com (vpn-48-80.rdu2.redhat.com [10.10.48.80]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id t8IF4gwd011024; Fri, 18 Sep 2015 11:04:49 -0400 From: John Snow To: qemu-devel@nongnu.org Date: Fri, 18 Sep 2015 11:04:41 -0400 Message-Id: <1442588681-18564-12-git-send-email-jsnow@redhat.com> In-Reply-To: <1442588681-18564-1-git-send-email-jsnow@redhat.com> References: <1442588681-18564-1-git-send-email-jsnow@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: peter.maydell@linaro.org, jsnow@redhat.com Subject: [Qemu-devel] [PULL 11/11] ahci: clean up initial d2h semantics X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org with write_fis_d2h and signature generation tidied up, let's adjust the initial d2h semantics to make more sense. The initial d2h is considered delivered if there is guest memory to save it to. Signed-off-by: John Snow Reviewed-by: Stefan Hajnoczi Message-id: 1441140641-17631-5-git-send-email-jsnow@redhat.com --- hw/ide/ahci.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index ea87f5a..796be15 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -46,7 +46,7 @@ do { \ static void check_cmd(AHCIState *s, int port); static int handle_cmd(AHCIState *s, int port, uint8_t slot); static void ahci_reset_port(AHCIState *s, int port); -static void ahci_write_fis_d2h(AHCIDevice *ad); +static bool ahci_write_fis_d2h(AHCIDevice *ad); static void ahci_init_d2h(AHCIDevice *ad); static int ahci_dma_prepare_buf(IDEDMA *dma, int32_t limit); static bool ahci_map_clb_address(AHCIDevice *ad); @@ -295,7 +295,6 @@ static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val) if ((pr->cmd & PORT_CMD_FIS_ON) && !s->dev[port].init_d2h_sent) { ahci_init_d2h(&s->dev[port]); - s->dev[port].init_d2h_sent = true; } check_cmd(s, port); @@ -541,14 +540,19 @@ static void ahci_init_d2h(AHCIDevice *ad) IDEState *ide_state = &ad->port.ifs[0]; AHCIPortRegs *pr = &ad->port_regs; - /* We're emulating receiving the first Reg H2D Fis from the device; - * Update the SIG register, but otherwise proceed as normal. */ - pr->sig = (ide_state->hcyl << 24) | - (ide_state->lcyl << 16) | - (ide_state->sector << 8) | - (ide_state->nsector & 0xFF); + if (ad->init_d2h_sent) { + return; + } - ahci_write_fis_d2h(ad); + if (ahci_write_fis_d2h(ad)) { + ad->init_d2h_sent = true; + /* We're emulating receiving the first Reg H2D Fis from the device; + * Update the SIG register, but otherwise proceed as normal. */ + pr->sig = (ide_state->hcyl << 24) | + (ide_state->lcyl << 16) | + (ide_state->sector << 8) | + (ide_state->nsector & 0xFF); + } } static void ahci_set_signature(AHCIDevice *ad, uint32_t sig) @@ -750,7 +754,7 @@ static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len) ahci_trigger_irq(ad->hba, ad, PORT_IRQ_PIOS_FIS); } -static void ahci_write_fis_d2h(AHCIDevice *ad) +static bool ahci_write_fis_d2h(AHCIDevice *ad) { AHCIPortRegs *pr = &ad->port_regs; uint8_t *d2h_fis; @@ -758,7 +762,7 @@ static void ahci_write_fis_d2h(AHCIDevice *ad) IDEState *s = &ad->port.ifs[0]; if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { - return; + return false; } d2h_fis = &ad->res_fis[RES_FIS_RFIS]; @@ -791,6 +795,7 @@ static void ahci_write_fis_d2h(AHCIDevice *ad) } ahci_trigger_irq(ad->hba, ad, PORT_IRQ_D2H_REG_FIS); + return true; } static int prdt_tbl_entry_size(const AHCI_SG *tbl)