From patchwork Mon Sep 14 10:51:28 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergey Fedorov X-Patchwork-Id: 517359 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id F0DCF14076E for ; Mon, 14 Sep 2015 20:56:18 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=sAWgAuVs; dkim-atps=neutral Received: from localhost ([::1]:39781 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZbRQm-0003kR-TX for incoming@patchwork.ozlabs.org; Mon, 14 Sep 2015 06:56:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53003) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZbRMm-0006DP-Vz for qemu-devel@nongnu.org; Mon, 14 Sep 2015 06:52:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZbRMj-0002az-IA for qemu-devel@nongnu.org; Mon, 14 Sep 2015 06:52:08 -0400 Received: from mail-la0-x22c.google.com ([2a00:1450:4010:c03::22c]:35548) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZbRMj-0002aR-79 for qemu-devel@nongnu.org; Mon, 14 Sep 2015 06:52:05 -0400 Received: by lagj9 with SMTP id j9so85076146lag.2 for ; Mon, 14 Sep 2015 03:52:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=Da2gvppl/a/O/KQaW9LguqsluVIv5P+QGReciUxwgac=; b=sAWgAuVsikpZqlb4GJW/elxp7MOVvXTHdB1Isr5z9G3UDi1MEcmMvdwvfck2vciMOS 639i+oWSG9jQmbxci+ysOrOrksH/rICgAVZz2cx4utHOhoOi93t0uZNlmZq3CiLRILFH UXLqTrqOC8Cpm7I3WO2dsEmiekH3iJmfOCm+wqpLWSAOq01xkJxaY6QF24k4oI18MD8L 71reo6T0z3fQjVvQiJZLmlbIU/UcjTwiNRMhHnq3Ze0pULM2OMQx/SwI+pJHh46yOppo XmTD83eARFbNmLMhfBaCpGm2jjz0dxZjXEWdKRE5SOSc+gM8Da6p0sI6BqONlVVOPjfJ UnWQ== X-Received: by 10.152.28.9 with SMTP id x9mr4151151lag.73.1442227924599; Mon, 14 Sep 2015 03:52:04 -0700 (PDT) Received: from sfedorov-laptop.smware.local ([213.243.91.10]) by smtp.gmail.com with ESMTPSA id ug2sm2268728lbc.34.2015.09.14.03.52.03 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 14 Sep 2015 03:52:03 -0700 (PDT) From: Sergey Fedorov To: qemu-devel@nongnu.org Date: Mon, 14 Sep 2015 13:51:28 +0300 Message-Id: <1442227888-11467-1-git-send-email-serge.fdrv@gmail.com> X-Mailer: git-send-email 1.9.1 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:4010:c03::22c Cc: Sergey Fedorov , Peter Maydell Subject: [Qemu-devel] [PATCH] target-arm: fix CPU breakpoint handling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org A QEMU breakpoint match is not definitely an architectural breakpoint match. If an exception is generated unconditionally during translation, it is hardly possible to ignore it in the debug exceptoin hanlder. Generate a call to helper to check CPU breakpoints and raise an exception only if any breakpoint architecturally matches. Signed-off-by: Sergey Fedorov --- target-arm/helper.h | 2 ++ target-arm/op_helper.c | 20 +++++++++++++++++++- target-arm/translate-a64.c | 12 +++++++----- target-arm/translate.c | 12 +++++++----- 4 files changed, 35 insertions(+), 11 deletions(-) diff --git a/target-arm/helper.h b/target-arm/helper.h index 827b33d..c2a85c7 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -54,6 +54,8 @@ DEF_HELPER_1(yield, void, env) DEF_HELPER_1(pre_hvc, void, env) DEF_HELPER_2(pre_smc, void, env, i32) +DEF_HELPER_1(check_breakpoints, void, env) + DEF_HELPER_3(cpsr_write, void, env, i32, i32) DEF_HELPER_1(cpsr_read, i32, env) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index b298e57..24dcefd 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -877,6 +877,15 @@ bool arm_debug_check_watchpoint(CPUState *cs) return check_watchpoints(cpu); } +void HELPER(check_breakpoints)(CPUARMState *env) +{ + ARMCPU *cpu = arm_env_get_cpu(env); + + if (check_breakpoints(cpu)) { + HELPER(exception_internal(env, EXCP_DEBUG)); + } +} + void arm_debug_excp_handler(CPUState *cs) { /* Called by core code when a watchpoint or breakpoint fires; @@ -904,7 +913,16 @@ void arm_debug_excp_handler(CPUState *cs) arm_debug_target_el(env)); } } else { - if (check_breakpoints(cpu)) { + CPUBreakpoint *bp; + uint64_t pc = is_a64(env) ? env->pc : env->regs[15]; + + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { + if (bp->pc == pc && !(bp->flags & BP_CPU)) { + return; + } + } + + { bool same_el = (arm_debug_target_el(env) == arm_current_el(env)); if (extended_addresses_enabled(env)) { env->exception.fsr = (1 << 9) | 0x22; diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 5c13e15..a5927fd 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -11000,11 +11000,13 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - /* Advance PC so that clearing the breakpoint will - invalidate this TB. */ - dc->pc += 2; - goto done_generating; + if (bp->flags & BP_CPU) { + gen_helper_check_breakpoints(cpu_env); + break; + } else { + gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + goto done_generating; + } } } } diff --git a/target-arm/translate.c b/target-arm/translate.c index e27634f..7e2d214 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -11292,11 +11292,13 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - /* Advance PC so that clearing the breakpoint will - invalidate this TB. */ - dc->pc += 2; - goto done_generating; + if (bp->flags & BP_CPU) { + gen_helper_check_breakpoints(cpu_env); + break; + } else { + gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + goto done_generating; + } } } }