From patchwork Fri Sep 4 15:05:39 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 514611 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id E730B14029C for ; Sat, 5 Sep 2015 01:11:11 +1000 (AEST) Received: from localhost ([::1]:60578 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZXsdx-0000r8-PS for incoming@patchwork.ozlabs.org; Fri, 04 Sep 2015 11:11:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38009) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZXsZ9-0008T6-Ho for qemu-devel@nongnu.org; Fri, 04 Sep 2015 11:06:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZXsZ8-0000qS-8z for qemu-devel@nongnu.org; Fri, 04 Sep 2015 11:06:11 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:35023) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZXsZ8-0000iE-1T for qemu-devel@nongnu.org; Fri, 04 Sep 2015 11:06:10 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1ZXsYu-0006FE-Id for qemu-devel@nongnu.org; Fri, 04 Sep 2015 16:05:56 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 4 Sep 2015 16:05:39 +0100 Message-Id: <1441379156-23939-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1441379156-23939-1-git-send-email-peter.maydell@linaro.org> References: <1441379156-23939-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 10/27] target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org For the A64 instruction set, the semihosting call instruction is 'HLT 0xf000'. Wire this up to call do_arm_semihosting() if semihosting is enabled. Signed-off-by: Peter Maydell Reviewed-by: Christopher Covington Tested-by: Christopher Covington Message-id: 1439483745-28752-10-git-send-email-peter.maydell@linaro.org --- linux-user/main.c | 3 +++ target-arm/cpu.h | 1 + target-arm/helper-a64.c | 6 ++++++ target-arm/internals.h | 2 ++ target-arm/translate-a64.c | 24 ++++++++++++++++++++++-- 5 files changed, 34 insertions(+), 2 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index 2c9658e..06dd296 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -1052,6 +1052,9 @@ void cpu_loop(CPUARMState *env) queue_signal(env, info.si_signo, &info); } break; + case EXCP_SEMIHOST: + env->xregs[0] = do_arm_semihosting(env); + break; default: fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 0a25335..c794afc 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -56,6 +56,7 @@ #define EXCP_SMC 13 /* Secure Monitor Call */ #define EXCP_VIRQ 14 #define EXCP_VFIQ 15 +#define EXCP_SEMIHOST 16 /* semihosting call (A64 only) */ #define ARMV7M_EXCP_RESET 1 #define ARMV7M_EXCP_NMI 2 diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index 08c95a3..02fc9b4 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -514,6 +514,12 @@ void aarch64_cpu_do_interrupt(CPUState *cs) case EXCP_VFIQ: addr += 0x100; break; + case EXCP_SEMIHOST: + qemu_log_mask(CPU_LOG_INT, + "...handling as semihosting call 0x%" PRIx64 "\n", + env->xregs[0]); + env->xregs[0] = do_arm_semihosting(env); + return; default: cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); } diff --git a/target-arm/internals.h b/target-arm/internals.h index 924aff9..36a56aa 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -36,6 +36,7 @@ static inline bool excp_is_internal(int excp) || excp == EXCP_HALTED || excp == EXCP_EXCEPTION_EXIT || excp == EXCP_KERNEL_TRAP + || excp == EXCP_SEMIHOST || excp == EXCP_STREX; } @@ -58,6 +59,7 @@ static const char * const excnames[] = { [EXCP_SMC] = "Secure Monitor Call", [EXCP_VIRQ] = "Virtual IRQ", [EXCP_VFIQ] = "Virtual FIQ", + [EXCP_SEMIHOST] = "Semihosting call", }; static inline void arm_log_exception(int idx) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 5c13e15..529bb0c 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -30,6 +30,7 @@ #include "internals.h" #include "qemu/host-utils.h" +#include "exec/semihost.h" #include "exec/gen-icount.h" #include "exec/helper-proto.h" @@ -1553,8 +1554,27 @@ static void disas_exc(DisasContext *s, uint32_t insn) unallocated_encoding(s); break; } - /* HLT */ - unsupported_encoding(s, insn); + /* HLT. This has two purposes. + * Architecturally, it is an external halting debug instruction. + * Since QEMU doesn't implement external debug, we treat this as + * it is required for halting debug disabled: it will UNDEF. + * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction. + */ + if (semihosting_enabled() && imm16 == 0xf000) { +#ifndef CONFIG_USER_ONLY + /* In system mode, don't allow userspace access to semihosting, + * to provide some semblance of security (and for consistency + * with our 32-bit semihosting). + */ + if (s->current_el == 0) { + unsupported_encoding(s, insn); + break; + } +#endif + gen_exception_internal_insn(s, 0, EXCP_SEMIHOST); + } else { + unsupported_encoding(s, insn); + } break; case 5: if (op2_ll < 1 || op2_ll > 3) {