From patchwork Mon Aug 24 16:17:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 510149 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id CCCE1140280 for ; Tue, 25 Aug 2015 02:20:29 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=s0XsKb3G; dkim-atps=neutral Received: from localhost ([::1]:54972 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZTuTz-0005IA-LN for incoming@patchwork.ozlabs.org; Mon, 24 Aug 2015 12:20:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37554) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZTuSc-0002nf-AQ for qemu-devel@nongnu.org; Mon, 24 Aug 2015 12:19:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZTuSb-0002y3-1R for qemu-devel@nongnu.org; Mon, 24 Aug 2015 12:19:02 -0400 Received: from mail-qg0-x22a.google.com ([2607:f8b0:400d:c04::22a]:33307) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZTuSa-0002xq-Te for qemu-devel@nongnu.org; Mon, 24 Aug 2015 12:19:00 -0400 Received: by qgeh99 with SMTP id h99so30331266qge.0 for ; Mon, 24 Aug 2015 09:19:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=JF0pIXzxTgLp3H75ynNPwFmUQ4tzMhcEP3DunHQR6UI=; b=s0XsKb3GTaAo2+j9plsCToBs85x8UNhau10kTGd0F7gx7AT9qV433WAqJlVnzfsR09 o8whoG7Tt3wPWI+dycgBpOofX6p0l4pTdn38s3f74JZb8nfo6Bh86I5Oh50hMbDGzfFB Yvd3qij/9+Rg7JdX5Ma7jdG3HcHUvzOcGbsGVAKWBEHvaSa3PlvbtO59SjwtWG+qpsWm e7WJe6uCfd5oUCkWpoOKgt/BNOGKW93l+OFzNvMKezcKc/Yom84a5dyzIJlKZXQIQtJq b+Ob03iI4+NeQUP0QNq84FZy0jG4ciSK1k1Zo5sigHrXn+UgbZlBLYMnY66EE7WRJHPG TvGA== X-Received: by 10.140.233.210 with SMTP id e201mr58193314qhc.88.1440433140662; Mon, 24 Aug 2015 09:19:00 -0700 (PDT) Received: from bigtime.com ([75.147.178.105]) by smtp.gmail.com with ESMTPSA id g76sm11445818qhc.33.2015.08.24.09.18.59 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 24 Aug 2015 09:19:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Aug 2015 09:17:41 -0700 Message-Id: <1440433079-14458-16-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1440433079-14458-1-git-send-email-rth@twiddle.net> References: <1440433079-14458-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c04::22a Cc: walt@tilera.com, cmetcalf@ezchip.com, xili_gchen_5257@hotmail.com, peter.maydell@linaro.org Subject: [Qemu-devel] [PATCH v14 15/33] target-tilegx: Handle arithmetic instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target-tilegx/translate.c | 95 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 89 insertions(+), 6 deletions(-) diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index 066d351..090c006 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -160,6 +160,23 @@ static TCGv dest_gr(DisasContext *dc, unsigned reg) return dc->wb[n].val = tcg_temp_new_i64(); } +static void gen_saturate_op(TCGv tdest, TCGv tsrca, TCGv tsrcb, + void (*operate)(TCGv, TCGv, TCGv)) +{ + TCGv t0 = tcg_temp_new(); + + tcg_gen_ext32s_tl(tdest, tsrca); + tcg_gen_ext32s_tl(t0, tsrcb); + operate(tdest, tdest, t0); + + tcg_gen_movi_tl(t0, 0x7fffffff); + tcg_gen_movcond_tl(TCG_COND_GT, tdest, tdest, t0, t0, tdest); + tcg_gen_movi_tl(t0, -0x80000000LL); + tcg_gen_movcond_tl(TCG_COND_LT, tdest, tdest, t0, t0, tdest); + + tcg_temp_free(t0); +} + static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext, unsigned dest, unsigned srca) { @@ -277,15 +294,24 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, switch (opext) { case OE_RRR(ADDXSC, 0, X0): case OE_RRR(ADDXSC, 0, X1): + gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_add_tl); + mnemonic = "addxsc"; + break; case OE_RRR(ADDX, 0, X0): case OE_RRR(ADDX, 0, X1): case OE_RRR(ADDX, 0, Y0): case OE_RRR(ADDX, 0, Y1): + tcg_gen_add_tl(tdest, tsrca, tsrcb); + tcg_gen_ext32s_tl(tdest, tdest); + mnemonic = "addx"; + break; case OE_RRR(ADD, 0, X0): case OE_RRR(ADD, 0, X1): case OE_RRR(ADD, 0, Y0): case OE_RRR(ADD, 0, Y1): - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; + tcg_gen_add_tl(tdest, tsrca, tsrcb); + mnemonic = "add"; + break; case OE_RRR(AND, 0, X0): case OE_RRR(AND, 0, X1): case OE_RRR(AND, 5, Y0): @@ -422,30 +448,58 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, case OE_RRR(ROTL, 0, X1): case OE_RRR(ROTL, 6, Y0): case OE_RRR(ROTL, 6, Y1): + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; case OE_RRR(SHL1ADDX, 0, X0): case OE_RRR(SHL1ADDX, 0, X1): case OE_RRR(SHL1ADDX, 7, Y0): case OE_RRR(SHL1ADDX, 7, Y1): + tcg_gen_shli_tl(tdest, tsrca, 1); + tcg_gen_add_tl(tdest, tdest, tsrcb); + tcg_gen_ext32s_tl(tdest, tdest); + mnemonic = "shl1addx"; + break; case OE_RRR(SHL1ADD, 0, X0): case OE_RRR(SHL1ADD, 0, X1): case OE_RRR(SHL1ADD, 1, Y0): case OE_RRR(SHL1ADD, 1, Y1): + tcg_gen_shli_tl(tdest, tsrca, 1); + tcg_gen_add_tl(tdest, tdest, tsrcb); + mnemonic = "shl1add"; + break; case OE_RRR(SHL2ADDX, 0, X0): case OE_RRR(SHL2ADDX, 0, X1): case OE_RRR(SHL2ADDX, 7, Y0): case OE_RRR(SHL2ADDX, 7, Y1): + tcg_gen_shli_tl(tdest, tsrca, 2); + tcg_gen_add_tl(tdest, tdest, tsrcb); + tcg_gen_ext32s_tl(tdest, tdest); + mnemonic = "shl2addx"; + break; case OE_RRR(SHL2ADD, 0, X0): case OE_RRR(SHL2ADD, 0, X1): case OE_RRR(SHL2ADD, 1, Y0): case OE_RRR(SHL2ADD, 1, Y1): + tcg_gen_shli_tl(tdest, tsrca, 2); + tcg_gen_add_tl(tdest, tdest, tsrcb); + mnemonic = "shl2add"; + break; case OE_RRR(SHL3ADDX, 0, X0): case OE_RRR(SHL3ADDX, 0, X1): case OE_RRR(SHL3ADDX, 7, Y0): case OE_RRR(SHL3ADDX, 7, Y1): + tcg_gen_shli_tl(tdest, tsrca, 3); + tcg_gen_add_tl(tdest, tdest, tsrcb); + tcg_gen_ext32s_tl(tdest, tdest); + mnemonic = "shl3addx"; + break; case OE_RRR(SHL3ADD, 0, X0): case OE_RRR(SHL3ADD, 0, X1): case OE_RRR(SHL3ADD, 1, Y0): case OE_RRR(SHL3ADD, 1, Y1): + tcg_gen_shli_tl(tdest, tsrca, 3); + tcg_gen_add_tl(tdest, tdest, tsrcb); + mnemonic = "shl3add"; + break; case OE_RRR(SHLX, 0, X0): case OE_RRR(SHLX, 0, X1): case OE_RRR(SHL, 0, X0): @@ -471,16 +525,27 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, case OE_RRR(STNT4, 0, X1): case OE_RRR(STNT, 0, X1): case OE_RRR(ST, 0, X1): + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; case OE_RRR(SUBXSC, 0, X0): case OE_RRR(SUBXSC, 0, X1): + gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_sub_tl); + mnemonic = "subxsc"; + break; case OE_RRR(SUBX, 0, X0): case OE_RRR(SUBX, 0, X1): case OE_RRR(SUBX, 0, Y0): case OE_RRR(SUBX, 0, Y1): + tcg_gen_sub_tl(tdest, tsrca, tsrcb); + tcg_gen_ext32s_tl(tdest, tdest); + mnemonic = "subx"; + break; case OE_RRR(SUB, 0, X0): case OE_RRR(SUB, 0, X1): case OE_RRR(SUB, 0, Y0): case OE_RRR(SUB, 0, Y1): + tcg_gen_sub_tl(tdest, tsrca, tsrcb); + mnemonic = "sub"; + break; case OE_RRR(V1ADDUC, 0, X0): case OE_RRR(V1ADDUC, 0, X1): case OE_RRR(V1ADD, 0, X0): @@ -640,11 +705,21 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext, const char *mnemonic; switch (opext) { + case OE(ADDI_OPCODE_Y0, 0, Y0): + case OE(ADDI_OPCODE_Y1, 0, Y1): case OE_IM(ADDI, X0): case OE_IM(ADDI, X1): + tcg_gen_addi_tl(tdest, tsrca, imm); + mnemonic = "addi"; + break; + case OE(ADDXI_OPCODE_Y0, 0, Y0): + case OE(ADDXI_OPCODE_Y1, 0, Y1): case OE_IM(ADDXI, X0): case OE_IM(ADDXI, X1): - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; + tcg_gen_addi_tl(tdest, tsrca, imm); + tcg_gen_ext32s_tl(tdest, tdest); + mnemonic = "addxi"; + break; case OE(ANDI_OPCODE_Y0, 0, Y0): case OE(ANDI_OPCODE_Y1, 0, Y1): case OE_IM(ANDI, X0): @@ -753,20 +828,28 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext, case OE_SH(V2SHRUI, X0): case OE_SH(V2SHRUI, X1): - case OE(ADDI_OPCODE_Y0, 0, Y0): - case OE(ADDI_OPCODE_Y1, 0, Y1): case OE(ADDLI_OPCODE_X0, 0, X0): case OE(ADDLI_OPCODE_X1, 0, X1): - case OE(ADDXI_OPCODE_Y0, 0, Y0): - case OE(ADDXI_OPCODE_Y1, 0, Y1): + tcg_gen_addi_tl(tdest, tsrca, imm); + mnemonic = "addli"; + break; case OE(ADDXLI_OPCODE_X0, 0, X0): case OE(ADDXLI_OPCODE_X1, 0, X1): + tcg_gen_addi_tl(tdest, tsrca, imm); + tcg_gen_ext32s_tl(tdest, tdest); + mnemonic = "addxli"; + break; case OE(CMPEQI_OPCODE_Y0, 0, Y0): case OE(CMPEQI_OPCODE_Y1, 0, Y1): case OE(CMPLTSI_OPCODE_Y0, 0, Y0): case OE(CMPLTSI_OPCODE_Y1, 0, Y1): + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; case OE(SHL16INSLI_OPCODE_X0, 0, X0): case OE(SHL16INSLI_OPCODE_X1, 0, X1): + tcg_gen_shli_tl(tdest, tsrca, 16); + tcg_gen_ori_tl(tdest, tdest, imm & 0xffff); + mnemonic = "shl16insli"; + break; default: return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;