From patchwork Wed Aug 12 14:24:00 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guenter Roeck X-Patchwork-Id: 506661 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42DCB14018C for ; Thu, 13 Aug 2015 00:24:32 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=roeck-us.net header.i=@roeck-us.net header.b=3HZw/G24; dkim-atps=neutral Received: from localhost ([::1]:38910 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZPWxC-0001vZ-Dt for incoming@patchwork.ozlabs.org; Wed, 12 Aug 2015 10:24:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60644) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZPWwv-0001db-Kq for qemu-devel@nongnu.org; Wed, 12 Aug 2015 10:24:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZPWwq-00035h-Pg for qemu-devel@nongnu.org; Wed, 12 Aug 2015 10:24:13 -0400 Received: from bh-25.webhostbox.net ([208.91.199.152]:44334) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZPWwq-00035Q-KR for qemu-devel@nongnu.org; Wed, 12 Aug 2015 10:24:08 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=roeck-us.net; s=default; h=Message-Id:Date:Subject:Cc:To:From; bh=dI+hon3fNo83PWeA35qf7CkZHdED4N0bCESl0FfAgK0=; b=3HZw/G24z3RYaYRPJ3/LRd4uxdso3bz1PRb2OnCx7A4Vd3UlxfferKWP4XCYnXq7aMee7bBT+ZAGueBjBfw4rYh8QQSCpVfpPW2A8opc+6Aow+GlE3umY4Ufk97XJGaRlPaAmkf+8KykoVCYIdCW7xwBHdOw1cCmzzZEgwWtoUg=; Received: from 108-223-40-66.lightspeed.sntcca.sbcglobal.net ([108.223.40.66]:58242 helo=localhost) by bh-25.webhostbox.net with esmtpa (Exim 4.85) (envelope-from ) id 1ZPWwo-003Is0-79; Wed, 12 Aug 2015 14:24:07 +0000 From: Guenter Roeck To: qemu-devel@nongnu.org Date: Wed, 12 Aug 2015 07:24:00 -0700 Message-Id: <1439389440-22371-1-git-send-email-linux@roeck-us.net> X-Mailer: git-send-email 2.1.4 X-Authenticated_sender: guenter@roeck-us.net X-OutGoing-Spam-Status: No, score=-1.0 X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - bh-25.webhostbox.net X-AntiAbuse: Original Domain - nongnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - roeck-us.net X-Get-Message-Sender-Via: bh-25.webhostbox.net: authenticated_id: guenter@roeck-us.net X-Source: X-Source-Args: X-Source-Dir: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 208.91.199.152 Cc: Peter Crosthwaite , Guenter Roeck Subject: [Qemu-devel] [PATCH] hw/misc/zynq_slcr: Change CPU clock rate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The Linux kernel only accepts 333334 Khz and 666667 Khz clock rates, and may crash if the actual clock rate is too low. The clock rate used to be (ps-clk-frequency * 26 / 4), which resulted in a CPU frequency of 216666 Khz if ps-clk-frequency was set to 33333333 Hz. Change it to (ps-clk-frequency * 20 / 2) = 333333 Khz to make Linux happy. Signed-off-by: Guenter Roeck --- hw/misc/zynq_slcr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index 964f253..d3e1ce0 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -189,7 +189,7 @@ static void zynq_slcr_reset(DeviceState *d) s->regs[LOCKSTA] = 1; /* 0x100 - 0x11C */ - s->regs[ARM_PLL_CTRL] = 0x0001A008; + s->regs[ARM_PLL_CTRL] = 0x00014008; s->regs[DDR_PLL_CTRL] = 0x0001A008; s->regs[IO_PLL_CTRL] = 0x0001A008; s->regs[PLL_STATUS] = 0x0000003F; @@ -198,7 +198,7 @@ static void zynq_slcr_reset(DeviceState *d) s->regs[IO_PLL_CFG] = 0x00014000; /* 0x120 - 0x16C */ - s->regs[ARM_CLK_CTRL] = 0x1F000400; + s->regs[ARM_CLK_CTRL] = 0x1F000200; s->regs[DDR_CLK_CTRL] = 0x18400003; s->regs[DCI_CLK_CTRL] = 0x01E03201; s->regs[APER_CLK_CTRL] = 0x01FFCCCD;