| Message ID | 1438281398-18746-5-git-send-email-peter.maydell@linaro.org |
|---|---|
| State | New |
| Headers | show |
On Thu, Jul 30, 2015 at 07:36:38PM +0100, Peter Maydell wrote: > We already implemented ACTLR_EL1; add the missing ACTLR_EL2 and > ACTLR_EL3, for consistency. > > Since we don't currently have any CPUs that need the EL2/EL3 > versions to reset to non-zero values, implement as RAZ/WI. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > --- > target-arm/helper.c | 21 +++++++++++++++------ > 1 file changed, 15 insertions(+), 6 deletions(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index d286680..b0b1a22 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -3637,13 +3637,22 @@ void register_cp_regs_for_features(ARMCPU *cpu) > } > > if (arm_feature(env, ARM_FEATURE_AUXCR)) { > - ARMCPRegInfo auxcr = { > - .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, > - .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, > - .access = PL1_RW, .type = ARM_CP_CONST, > - .resetvalue = cpu->reset_auxcr > + ARMCPRegInfo auxcr_reginfo[] = { > + { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, > + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, > + .access = PL1_RW, .type = ARM_CP_CONST, > + .resetvalue = cpu->reset_auxcr }, > + { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, > + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, > + .access = PL2_RW, .type = ARM_CP_CONST, > + .resetvalue = 0 }, > + { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, > + .access = PL3_RW, .type = ARM_CP_CONST, > + .resetvalue = 0 }, > + REGINFO_SENTINEL > }; > - define_one_arm_cp_reg(cpu, &auxcr); > + define_arm_cp_regs(cpu, auxcr_reginfo); > } > > if (arm_feature(env, ARM_FEATURE_CBAR)) { > -- > 1.9.1 >
diff --git a/target-arm/helper.c b/target-arm/helper.c index d286680..b0b1a22 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3637,13 +3637,22 @@ void register_cp_regs_for_features(ARMCPU *cpu) } if (arm_feature(env, ARM_FEATURE_AUXCR)) { - ARMCPRegInfo auxcr = { - .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, - .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, - .access = PL1_RW, .type = ARM_CP_CONST, - .resetvalue = cpu->reset_auxcr + ARMCPRegInfo auxcr_reginfo[] = { + { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, + .access = PL1_RW, .type = ARM_CP_CONST, + .resetvalue = cpu->reset_auxcr }, + { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, + .access = PL2_RW, .type = ARM_CP_CONST, + .resetvalue = 0 }, + { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, + .access = PL3_RW, .type = ARM_CP_CONST, + .resetvalue = 0 }, + REGINFO_SENTINEL }; - define_one_arm_cp_reg(cpu, &auxcr); + define_arm_cp_regs(cpu, auxcr_reginfo); } if (arm_feature(env, ARM_FEATURE_CBAR)) {
We already implemented ACTLR_EL1; add the missing ACTLR_EL2 and ACTLR_EL3, for consistency. Since we don't currently have any CPUs that need the EL2/EL3 versions to reset to non-zero values, implement as RAZ/WI. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target-arm/helper.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-)