From patchwork Mon Jul 27 10:56:08 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 500334 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3419D1402E8 for ; Mon, 27 Jul 2015 20:57:05 +1000 (AEST) Received: from localhost ([::1]:52660 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZJg5f-0003Br-5s for incoming@patchwork.ozlabs.org; Mon, 27 Jul 2015 06:57:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38942) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZJg4x-00022j-Tt for qemu-devel@nongnu.org; Mon, 27 Jul 2015 06:56:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZJg4v-0005eO-F7 for qemu-devel@nongnu.org; Mon, 27 Jul 2015 06:56:19 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:42637) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZJg4v-0005dI-7E for qemu-devel@nongnu.org; Mon, 27 Jul 2015 06:56:17 -0400 Received: from weber.rr44.fr ([2001:bc8:30d7:120:7e05:7ff:fe0d:f152]) by hall.aurel32.net with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.84) (envelope-from ) id 1ZJg4t-0005HB-Fq; Mon, 27 Jul 2015 12:56:15 +0200 Received: from aurel32 by weber.rr44.fr with local (Exim 4.85) (envelope-from ) id 1ZJg4s-000241-HJ; Mon, 27 Jul 2015 12:56:14 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Mon, 27 Jul 2015 12:56:08 +0200 Message-Id: <1437994568-7825-13-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1437994568-7825-1-git-send-email-aurelien@aurel32.net> References: <1437994568-7825-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:bc8:30d7:100::1 Cc: Paolo Bonzini , Aurelien Jarno , Richard Henderson Subject: [Qemu-devel] [PATCH v2 for-2.5 12/12] tcg: update README about size changing ops X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Cc: Richard Henderson Signed-off-by: Aurelien Jarno --- tcg/README | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/tcg/README b/tcg/README index 61b3899..a22f251 100644 --- a/tcg/README +++ b/tcg/README @@ -466,13 +466,25 @@ On a 32 bit target, all 64 bit operations are converted to 32 bits. A few specific operations must be implemented to allow it (see add2_i32, sub2_i32, brcond2_i32). +On a 64 bit target, the values are transfered between 32 and 64-bit +registers using the following ops: +- trunc_shr_i64_i32 +- ext_i32_i64 +- extu_i32_i64 + +They ensure that the values are correctly truncated or extended when +moved from a 32-bit to a 64-bit register or vice-versa. Note that the +trunc_shr_i64_i32 is an optional op. It is not necessary to implement +it if all the following conditions are met: +- 64-bit registers can hold 32-bit values +- 32-bit values in a 64-bit register do not need to stay zero or + sign extended +- all 32-bit TCG ops ignore the high part of 64-bit registers + Floating point operations are not supported in this version. A previous incarnation of the code generator had full support of them, but it is better to concentrate on integer operations first. -On a 64 bit target, no assumption is made in TCG about the storage of -the 32 bit values in 64 bit registers. - 4.2) Constraints GCC like constraints are used to define the constraints of every