From patchwork Thu Jul 16 04:00:45 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen HanXiao X-Patchwork-Id: 496550 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 14FE1140778 for ; Thu, 16 Jul 2015 14:16:47 +1000 (AEST) Received: from localhost ([::1]:38305 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFabF-0001Ni-6z for incoming@patchwork.ozlabs.org; Thu, 16 Jul 2015 00:16:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33789) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFaUm-0006cp-C6 for qemu-devel@nongnu.org; Thu, 16 Jul 2015 00:10:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZFaUi-0005Dv-FK for qemu-devel@nongnu.org; Thu, 16 Jul 2015 00:10:04 -0400 Received: from [59.151.112.132] (port=37927 helo=heian.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFaUe-00053K-02 for qemu-devel@nongnu.org; Thu, 16 Jul 2015 00:10:00 -0400 X-IronPort-AV: E=Sophos;i="5.13,665,1427731200"; d="scan'208";a="98504032" Received: from bogon (HELO edo.cn.fujitsu.com) ([10.167.33.5]) by heian.cn.fujitsu.com with ESMTP; 16 Jul 2015 12:13:07 +0800 Received: from G08CNEXCHPEKD01.g08.fujitsu.local (localhost.localdomain [127.0.0.1]) by edo.cn.fujitsu.com (8.14.3/8.13.1) with ESMTP id t6G47ZbL003864; Thu, 16 Jul 2015 12:07:35 +0800 Received: from localhost.local (10.167.225.26) by G08CNEXCHPEKD01.g08.fujitsu.local (10.167.33.89) with Microsoft SMTP Server (TLS) id 14.3.181.6; Thu, 16 Jul 2015 12:09:21 +0800 From: Chen Hanxiao To: Alex Williamson , Date: Thu, 16 Jul 2015 12:00:45 +0800 Message-ID: <1437019253-17630-8-git-send-email-chenhanxiao@cn.fujitsu.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1437019253-17630-1-git-send-email-chenhanxiao@cn.fujitsu.com> References: <1437019253-17630-1-git-send-email-chenhanxiao@cn.fujitsu.com> MIME-Version: 1.0 X-Originating-IP: [10.167.225.26] X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 59.151.112.132 Cc: Chen Fan Subject: [Qemu-devel] [PATCH v12 07/15] vfio: add aer support for vfio device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Chen Fan Calling pcie_aer_init to initilize aer related registers for vfio device, then reload physical related registers to expose device capability. Signed-off-by: Chen Fan Signed-off-by: Chen Hanxiao --- hw/vfio/pci.c | 89 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 87 insertions(+), 2 deletions(-) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index d7dc8a1..5e24e9d 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -32,6 +32,7 @@ #include "hw/pci/msi.h" #include "hw/pci/msix.h" #include "hw/pci/pci.h" +#include "hw/pci/pci_bridge.h" #include "qemu-common.h" #include "qemu/error-report.h" #include "qemu/event_notifier.h" @@ -160,6 +161,8 @@ typedef struct VFIOPCIDevice { #define VFIO_FEATURE_ENABLE_VGA (1 << VFIO_FEATURE_ENABLE_VGA_BIT) #define VFIO_FEATURE_ENABLE_REQ_BIT 1 #define VFIO_FEATURE_ENABLE_REQ (1 << VFIO_FEATURE_ENABLE_REQ_BIT) +#define VFIO_FEATURE_ENABLE_AER_BIT 2 +#define VFIO_FEATURE_ENABLE_AER (1 << VFIO_FEATURE_ENABLE_AER_BIT) int32_t bootindex; uint8_t pm_cap; bool has_vga; @@ -2846,6 +2849,74 @@ static int vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t pos) return 0; } +static int vfio_setup_aer(VFIOPCIDevice *vdev, uint8_t cap_ver, + int pos, uint16_t size) +{ + PCIDevice *pdev = &vdev->pdev; + uint8_t *exp_cap = pdev->config + pdev->exp.exp_cap; + PCIDevice *dev_iter; + uint8_t type; + uint32_t severity, errcap; + int ret; + + if (!(vdev->features & VFIO_FEATURE_ENABLE_AER)) { + pcie_add_capability(pdev, PCI_EXT_CAP_ID_ERR, + cap_ver, pos, size); + return 0; + } + + dev_iter = pci_bridge_get_device(pdev->bus); + if (!dev_iter) { + goto error; + } + + while (dev_iter) { + type = pcie_cap_get_type(dev_iter); + if ((type != PCI_EXP_TYPE_ROOT_PORT && + type != PCI_EXP_TYPE_UPSTREAM && + type != PCI_EXP_TYPE_DOWNSTREAM)) { + goto error; + } + + if (!dev_iter->exp.aer_cap) { + goto error; + } + + dev_iter = pci_bridge_get_device(dev_iter->bus); + } + + errcap = vfio_pci_read_config(pdev, pdev->exp.aer_cap + PCI_ERR_CAP, 4); + /* + * The ability to record multiple headers is depending on + * the state of the Multiple Header Recording Capable bit and + * enabled by the Multiple Header Recording Enable bit. + */ + if ((errcap & PCI_ERR_CAP_MHRC) && + (errcap & PCI_ERR_CAP_MHRE)) { + pdev->exp.aer_log.log_max = PCIE_AER_LOG_MAX_DEFAULT; + } else { + pdev->exp.aer_log.log_max = 0; + } + + pcie_cap_deverr_init(pdev); + ret = pcie_aer_init(pdev, pos, size); + if (ret) { + return ret; + } + + /* load physical registers */ + severity = vfio_pci_read_config(pdev, + pdev->exp.aer_cap + PCI_ERR_UNCOR_SEVER, 4); + pci_long_test_and_clear_mask(exp_cap + PCI_ERR_UNCOR_SEVER, ~severity); + + return 0; + +error: + error_report("vfio: Unable to enable AER for device %s, parent bus " + "does not support AER signaling", vdev->vbasedev.name); + return -1; +} + static int vfio_add_ext_cap(VFIOPCIDevice *vdev) { PCIDevice *pdev = &vdev->pdev; @@ -2853,6 +2924,7 @@ static int vfio_add_ext_cap(VFIOPCIDevice *vdev) uint16_t cap_id, next, size; uint8_t cap_ver; uint8_t *config; + int ret = 0; /* * In order to avoid breaking config space, create a copy to @@ -2874,7 +2946,19 @@ static int vfio_add_ext_cap(VFIOPCIDevice *vdev) */ size = vfio_ext_cap_max_size(config, next); - pcie_add_capability(pdev, cap_id, cap_ver, next, size); + switch (cap_id) { + case PCI_EXT_CAP_ID_ERR: + ret = vfio_setup_aer(vdev, cap_ver, next, size); + break; + default: + pcie_add_capability(pdev, cap_id, cap_ver, next, size); + break; + } + + if (ret) { + goto out; + } + if (next == PCI_CONFIG_SPACE_SIZE) { /* Begin the rebuild, we should set the next offset zero. */ pci_set_long(pdev->config + next, PCI_EXT_CAP(cap_id, cap_ver, 0)); @@ -2884,8 +2968,9 @@ static int vfio_add_ext_cap(VFIOPCIDevice *vdev) pci_set_long(vdev->emulated_config_bits + next, 0xffffffff); } +out: g_free(config); - return 0; + return ret; } static int vfio_add_capabilities(VFIOPCIDevice *vdev)