From patchwork Fri Jul 10 11:10:02 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yongbok Kim X-Patchwork-Id: 493736 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8AF811402B8 for ; Fri, 10 Jul 2015 21:11:04 +1000 (AEST) Received: from localhost ([::1]:44105 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZDWCr-0002RK-8r for incoming@patchwork.ozlabs.org; Fri, 10 Jul 2015 07:11:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54131) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZDWCP-0001yZ-Ap for qemu-devel@nongnu.org; Fri, 10 Jul 2015 07:10:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZDWCK-0001EF-4q for qemu-devel@nongnu.org; Fri, 10 Jul 2015 07:10:33 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:20295) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZDWCJ-0001Di-Q1 for qemu-devel@nongnu.org; Fri, 10 Jul 2015 07:10:27 -0400 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 73D522AEE414D; Fri, 10 Jul 2015 12:10:21 +0100 (IST) Received: from hhmail02.hh.imgtec.org (10.100.10.20) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Fri, 10 Jul 2015 12:10:23 +0100 Received: from localhost.localdomain (192.168.14.192) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.235.1; Fri, 10 Jul 2015 12:10:23 +0100 From: Yongbok Kim To: Date: Fri, 10 Jul 2015 12:10:02 +0100 Message-ID: <1436526602-54425-1-git-send-email-yongbok.kim@imgtec.com> X-Mailer: git-send-email 1.7.5.4 MIME-Version: 1.0 X-Originating-IP: [192.168.14.192] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: serge.vakulenko@gmail.com, leon.alrae@imgtec.com, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH] target-mips: fix offset calculation for Interrupts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Correct computation of vector offsets for EXCP_EXT_INTERRUPT. For instance, if Cause.IV is 0 the vector offset should be 0x180. Simplify the finding vector number logic for the Vectored Interrupts. Signed-off-by: Yongbok Kim --- target-mips/helper.c | 47 ++++++++++++++++++++++------------------------- target-mips/op_helper.c | 2 -- 2 files changed, 22 insertions(+), 27 deletions(-) diff --git a/target-mips/helper.c b/target-mips/helper.c index 8e3204a..573bc1f 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -565,34 +565,31 @@ void mips_cpu_do_interrupt(CPUState *cs) break; case EXCP_EXT_INTERRUPT: cause = 0; - if (env->CP0_Cause & (1 << CP0Ca_IV)) - offset = 0x200; - - if (env->CP0_Config3 & ((1 << CP0C3_VInt) | (1 << CP0C3_VEIC))) { - /* Vectored Interrupts. */ - unsigned int spacing; - unsigned int vector; - unsigned int pending = (env->CP0_Cause & CP0Ca_IP_mask) >> 8; - - pending &= env->CP0_Status >> 8; - /* Compute the Vector Spacing. */ - spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & ((1 << 6) - 1); - spacing <<= 5; - - if (env->CP0_Config3 & (1 << CP0C3_VInt)) { - /* For VInt mode, the MIPS computes the vector internally. */ - for (vector = 7; vector > 0; vector--) { - if (pending & (1 << vector)) { - /* Found it. */ - break; + if (env->CP0_Cause & (1 << CP0Ca_IV)) { + uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) &0x1f; + + if ((env->CP0_Status & (1 << CP0St_BEV)) || spacing == 0) { + offset = 0x200; + } else { + uint32_t vector = 0; + uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) + >> CP0Ca_IP; + + if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { + /* For VEIC mode, the external interrupt controller feeds + * the vector through the CP0Cause IP lines. */ + vector = pending; + } else { + /* Vectored Interrupts + * Mask with Status.IM7-IM0 to get enabled interrupts. */ + pending &= (env->CP0_Status >> CP0St_IM) &0xff; + /* Find the highest-priority interrupt. */ + while (pending >>= 1) { + vector++; } } - } else { - /* For VEIC mode, the external interrupt controller feeds the - vector through the CP0Cause IP lines. */ - vector = pending; + offset = 0x200 + (vector * (spacing << 5)); } - offset = 0x200 + vector * spacing; } goto set_EPC; case EXCP_LTLBL: diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 2a9ddff..4c5d9dc 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -1432,7 +1432,6 @@ void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1) void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1) { - /* vectored interrupts not implemented, no performance counters. */ env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0); } @@ -1473,7 +1472,6 @@ target_ulong helper_mftc0_ebase(CPUMIPSState *env) void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1) { - /* vectored interrupts not implemented */ env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000); }