From patchwork Tue Jun 16 13:37:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Aurelio C. Remonda" X-Patchwork-Id: 484996 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id CB2E314027F for ; Tue, 16 Jun 2015 23:38:10 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=ezs32VrK; dkim-atps=neutral Received: from localhost ([::1]:40314 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4r44-0004ES-QE for incoming@patchwork.ozlabs.org; Tue, 16 Jun 2015 09:38:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41340) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4r3g-0003YQ-CO for qemu-devel@nongnu.org; Tue, 16 Jun 2015 09:37:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z4r3b-0006MF-9d for qemu-devel@nongnu.org; Tue, 16 Jun 2015 09:37:44 -0400 Received: from mail-qk0-x236.google.com ([2607:f8b0:400d:c09::236]:33024) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4r3b-0006Lj-5P for qemu-devel@nongnu.org; Tue, 16 Jun 2015 09:37:39 -0400 Received: by qkhu186 with SMTP id u186so8788916qkh.0 for ; Tue, 16 Jun 2015 06:37:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id; bh=d5yJT2wmRT2fG1Xpy6ppyIYSrs2xnVe6OfbU6H0JWZo=; b=ezs32VrKwNlSgiP71QclMR230J0JtrMBlQt9W5NQmPolSlwvJKencFtD6PrKCUzElI ofI6c2PHjK191mFSMlengNqGs3zlVyVZ8P6RsizX0Ke1RJ3p522uevbgsa6SCR+wJftC GKlwaHtlZpQCDNFvfSkmDZdiUjsCgfAR3rill6b3V60MswyuJInPFqN+0bGfcrxU2OSQ +e8c6XE6XhqDS+Wgs12/oHBu4q3+TQ5qdUHHsbRf8NAjNjTH1EDOpXPj/rVOzWTQDGzz 2Ed8mq6CVV/98M59TumpFhhfXt1qJT/uVXjtd88c4dUdt0B1qq+uIKJXF1DVdqDszqMw uGtg== X-Received: by 10.55.40.89 with SMTP id o86mr1139308qkh.6.1434461858606; Tue, 16 Jun 2015 06:37:38 -0700 (PDT) Received: from localhost.localdomain ([181.31.133.97]) by mx.google.com with ESMTPSA id w67sm443724qgw.41.2015.06.16.06.37.36 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 16 Jun 2015 06:37:38 -0700 (PDT) From: "Aurelio C. Remonda" To: qemu-devel@nongnu.org, ilg@livius.net, peter.maydell@linaro.org, martin.galvan@tallertechnologies.com, daniel.gutson@tallertechnologies.com Date: Tue, 16 Jun 2015 10:37:30 -0300 Message-Id: <1434461850-4104-1-git-send-email-aurelioremonda@gmail.com> X-Mailer: git-send-email 1.9.1 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c09::236 Subject: [Qemu-devel] [PATCH V4] Target-arm: Add the Cortex-M4 CPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds the Cortex-M4 CPU. The M4 is basically the same as the M3, the main differences being the DSP instructions and an optional FPU. Created an ARM_FEATURE_THUMB_DSP to be added to any non-M thumb2-compatible CPU that uses DSP instructions, and manually added it to the M4 in its initfn. The THUMB_DSP feature was created in a different patch along with the bit checking on each DSP instruction. Only no-FPU cortex-M4 is implemented here, cortex-M4F is not because the core target-arm code doesn't support the M-profile FPU model yet. Signed-off-by: Aurelio C. Remonda --- * Changes in V4: Commit message updated. Deleted unnecessary comment and added a blank line in cortex-M4 initfn. target-arm/cpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 4a888ab..d25a500 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -783,6 +783,15 @@ static void cortex_m3_initfn(Object *obj) cpu->midr = 0x410fc231; } +static void cortex_m4_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + cpu->midr = 0x410fc240; /* r0p0 */ +} static void arm_v7m_class_init(ObjectClass *oc, void *data) { CPUClass *cc = CPU_CLASS(oc); @@ -1185,6 +1194,8 @@ static const ARMCPUInfo arm_cpus[] = { { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, { .name = "cortex-m3", .initfn = cortex_m3_initfn, .class_init = arm_v7m_class_init }, + { .name = "cortex-m4", .initfn = cortex_m4_initfn, + .class_init = arm_v7m_class_init }, { .name = "cortex-a8", .initfn = cortex_a8_initfn }, { .name = "cortex-a9", .initfn = cortex_a9_initfn }, { .name = "cortex-a15", .initfn = cortex_a15_initfn },