From patchwork Mon Jun 15 17:24:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 484474 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D66D5140281 for ; Tue, 16 Jun 2015 03:37:49 +1000 (AEST) Received: from localhost ([::1]:35720 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4YKS-00053u-1i for incoming@patchwork.ozlabs.org; Mon, 15 Jun 2015 13:37:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60973) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4Y8J-0007k9-HX for qemu-devel@nongnu.org; Mon, 15 Jun 2015 13:25:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z4Y8G-0001VY-7O for qemu-devel@nongnu.org; Mon, 15 Jun 2015 13:25:15 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34471) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4Y8F-0001AA-Tr for qemu-devel@nongnu.org; Mon, 15 Jun 2015 13:25:12 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Z4Y82-0003W9-TY for qemu-devel@nongnu.org; Mon, 15 Jun 2015 18:24:58 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 15 Jun 2015 18:24:41 +0100 Message-Id: <1434389098-13430-12-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1434389098-13430-1-git-send-email-peter.maydell@linaro.org> References: <1434389098-13430-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 11/28] target-arm: Use the kernel's idea of MPIDR if we're using KVM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Pavel Fedin When we're using KVM, the kernel's internal idea of the MPIDR affinity fields must match the values we tell it for the guest vcpu cluster configuration in the device tree. Since at the moment the kernel doesn't support letting userspace tell it the correct affinity fields to use, we must read the kernel's view and reflect that back in the device tree. Signed-off-by: Shlomo Pongratz Signed-off-by: Pavel Fedin Message-id: 02f601d0a1e6$90c7d630$b2578290$@samsung.com [PMM: Use a local #define rather than a global variable for the TCG ARM_CPUS_PER_CLUSTER setting. Tweak a comment. Update the commit message.] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/virt.c | 2 +- target-arm/cpu-qom.h | 1 + target-arm/cpu.c | 12 ++++++++++++ target-arm/helper.c | 9 +++------ target-arm/kvm32.c | 15 +++++++++++++++ target-arm/kvm64.c | 15 +++++++++++++++ target-arm/psci.c | 19 +++++++++++++++++-- 7 files changed, 64 insertions(+), 9 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index dbe89c1..f1e85c8 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -311,7 +311,7 @@ static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi) "enable-method", "psci"); } - qemu_fdt_setprop_cell(vbi->fdt, nodename, "reg", cpu); + qemu_fdt_setprop_cell(vbi->fdt, nodename, "reg", armcpu->mp_affinity); g_free(nodename); } } diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index c80381d..24a4cfb 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -160,6 +160,7 @@ typedef struct ARMCPU { uint64_t id_aa64mmfr1; uint32_t dbgdidr; uint32_t clidr; + uint64_t mp_affinity; /* MP ID without feature bits */ /* The elements of this array are the CCSIDR values for each cache, * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. */ diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 4a888ab..34990ac 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -383,17 +383,29 @@ static inline void unset_feature(CPUARMState *env, int feature) env->features &= ~(1ULL << feature); } +#define ARM_CPUS_PER_CLUSTER 8 + static void arm_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); ARMCPU *cpu = ARM_CPU(obj); static bool inited; + uint32_t Aff1, Aff0; cs->env_ptr = &cpu->env; cpu_exec_init(&cpu->env); cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); + /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. + * We don't support setting cluster ID ([16..23]) (known as Aff2 + * in later ARM ARM versions), or any of the higher affinity level fields, + * so these bits always RAZ. + */ + Aff1 = cs->cpu_index / ARM_CPUS_PER_CLUSTER; + Aff0 = cs->cpu_index % ARM_CPUS_PER_CLUSTER; + cpu->mp_affinity = (Aff1 << 8) | Aff0; + #ifndef CONFIG_USER_ONLY /* Our inbound IRQ and FIQ lines */ if (kvm_enabled()) { diff --git a/target-arm/helper.c b/target-arm/helper.c index 16195b3..6a62d79 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2063,12 +2063,9 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] = { static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - CPUState *cs = CPU(arm_env_get_cpu(env)); - uint32_t mpidr = cs->cpu_index; - /* We don't support setting cluster ID ([8..11]) (known as Aff1 - * in later ARM ARM versions), or any of the higher affinity level fields, - * so these bits always RAZ. - */ + ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env)); + uint64_t mpidr = cpu->mp_affinity; + if (arm_feature(env, ARM_FEATURE_V7MP)) { mpidr |= (1U << 31); /* Cores which are uniprocessor (non-coherent) diff --git a/target-arm/kvm32.c b/target-arm/kvm32.c index 49b6bab..d7e7d68 100644 --- a/target-arm/kvm32.c +++ b/target-arm/kvm32.c @@ -153,10 +153,14 @@ bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx) } } +#define ARM_MPIDR_HWID_BITMASK 0xFFFFFF +#define ARM_CPU_ID_MPIDR 0, 0, 0, 5 + int kvm_arch_init_vcpu(CPUState *cs) { int ret; uint64_t v; + uint32_t mpidr; struct kvm_one_reg r; ARMCPU *cpu = ARM_CPU(cs); @@ -193,6 +197,17 @@ int kvm_arch_init_vcpu(CPUState *cs) return -EINVAL; } + /* + * When KVM is in use, PSCI is emulated in-kernel and not by qemu. + * Currently KVM has its own idea about MPIDR assignment, so we + * override our defaults with what we get from KVM. + */ + ret = kvm_get_one_reg(cs, ARM_CP15_REG32(ARM_CPU_ID_MPIDR), &mpidr); + if (ret) { + return ret; + } + cpu->mp_affinity = mpidr & ARM_MPIDR_HWID_BITMASK; + return kvm_arm_init_cpreg_list(cpu); } diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c index 93c1ca8..ac34f51 100644 --- a/target-arm/kvm64.c +++ b/target-arm/kvm64.c @@ -77,9 +77,13 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc) return true; } +#define ARM_MPIDR_HWID_BITMASK 0xFF00FFFFFFULL +#define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 + int kvm_arch_init_vcpu(CPUState *cs) { int ret; + uint64_t mpidr; ARMCPU *cpu = ARM_CPU(cs); if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE || @@ -107,6 +111,17 @@ int kvm_arch_init_vcpu(CPUState *cs) return ret; } + /* + * When KVM is in use, PSCI is emulated in-kernel and not by qemu. + * Currently KVM has its own idea about MPIDR assignment, so we + * override our defaults with what we get from KVM. + */ + ret = kvm_get_one_reg(cs, ARM64_SYS_REG(ARM_CPU_ID_MPIDR), &mpidr); + if (ret) { + return ret; + } + cpu->mp_affinity = mpidr & ARM_MPIDR_HWID_BITMASK; + return kvm_arm_init_cpreg_list(cpu); } diff --git a/target-arm/psci.c b/target-arm/psci.c index d8fafab..20e4cb6 100644 --- a/target-arm/psci.c +++ b/target-arm/psci.c @@ -72,6 +72,21 @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type) } } +static CPUState *get_cpu_by_id(uint64_t id) +{ + CPUState *cpu; + + CPU_FOREACH(cpu) { + ARMCPU *armcpu = ARM_CPU(cpu); + + if (armcpu->mp_affinity == id) { + return cpu; + } + } + + return NULL; +} + void arm_handle_psci_call(ARMCPU *cpu) { /* @@ -121,7 +136,7 @@ void arm_handle_psci_call(ARMCPU *cpu) switch (param[2]) { case 0: - target_cpu_state = qemu_get_cpu(mpidr & 0xff); + target_cpu_state = get_cpu_by_id(mpidr); if (!target_cpu_state) { ret = QEMU_PSCI_RET_INVALID_PARAMS; break; @@ -153,7 +168,7 @@ void arm_handle_psci_call(ARMCPU *cpu) context_id = param[3]; /* change to the cpu we are powering up */ - target_cpu_state = qemu_get_cpu(mpidr & 0xff); + target_cpu_state = get_cpu_by_id(mpidr); if (!target_cpu_state) { ret = QEMU_PSCI_RET_INVALID_PARAMS; break;