From patchwork Mon Jun 15 15:57:03 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 484414 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 24F251400A0 for ; Tue, 16 Jun 2015 02:04:00 +1000 (AEST) Received: from localhost ([::1]:35141 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4Wre-00040z-8o for incoming@patchwork.ozlabs.org; Mon, 15 Jun 2015 12:03:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48645) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4WlB-0000kg-Ql for qemu-devel@nongnu.org; Mon, 15 Jun 2015 11:57:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z4WlA-0003Jk-9i for qemu-devel@nongnu.org; Mon, 15 Jun 2015 11:57:17 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:101::1]:47744) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4Wl9-0003HG-Sz for qemu-devel@nongnu.org; Mon, 15 Jun 2015 11:57:16 -0400 Received: from weber.rr44.fr ([2001:470:d4ed:0:7e05:7ff:fe0d:f152]) by hall.aurel32.net with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.84) (envelope-from ) id 1Z4Wl7-0001RE-SC; Mon, 15 Jun 2015 17:57:13 +0200 Received: from aurel32 by weber.rr44.fr with local (Exim 4.85) (envelope-from ) id 1Z4Wl7-00009v-1M; Mon, 15 Jun 2015 17:57:13 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Mon, 15 Jun 2015 17:57:03 +0200 Message-Id: <1434383829-26451-5-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1434383829-26451-1-git-send-email-aurelien@aurel32.net> References: <1434383829-26451-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:bc8:30d7:101::1 Cc: Alexander Graf , Aurelien Jarno , Richard Henderson Subject: [Qemu-devel] [PATCH 04/10] target-s390x: fix setcc in TCG mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In TCG mode we should store the CC value in env->cc_op. However do it inconditionnaly because: - the tcg_enabled function is not inlined - it's probably faster to always store the value, especially given it is likely in the same cache line than env->psw.mask. Cc: Alexander Graf Cc: Richard Henderson Signed-off-by: Aurelien Jarno --- target-s390x/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h index 08a79dd..93f66f9 100644 --- a/target-s390x/cpu.h +++ b/target-s390x/cpu.h @@ -709,6 +709,7 @@ static inline void setcc(S390CPU *cpu, uint64_t cc) env->psw.mask &= ~(3ull << 44); env->psw.mask |= (cc & 3) << 44; + env->cc_op = cc; } typedef struct LowCore