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[79.178.119.223]) by mx.google.com with ESMTPSA id m10sm7089107wib.17.2015.06.04.09.40.41 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 04 Jun 2015 09:40:42 -0700 (PDT) From: Shlomo Pongratz To: qemu-devel@nongnu.org Date: Thu, 4 Jun 2015 19:40:37 +0300 Message-Id: <1433436037-5476-5-git-send-email-shlomopongratz@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1433436037-5476-1-git-send-email-shlomopongratz@gmail.com> References: <1433436037-5476-1-git-send-email-shlomopongratz@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:400c:c00::235 Cc: peter.maydell@linaro.org, eric.auger@linaro.org, p.fedin@samsung.com, shannon.zhao@linaro.org, ashoks@broadcom.com, imammedo@redhat.com Subject: [Qemu-devel] [PATCH RFC V3 4/4] Add virt-v3 machine that uses GIC-500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Pavel Fedin I would like to offer this, slightly improved implementation. The key thing is a new kernel_irqchip_type member in Machine class. Currently it it used only by virt machine for its internal purposes, however in future it is to be passed to KVM in kvm_irqchip_create(). The variable is defined as int in order to be architecture agnostic, for potential future users. Signed-off-by: Pavel Fedin --- hw/arm/virt.c | 159 +++++++++++++++++++++++++++++++++++++++++--------- include/hw/arm/virt.h | 4 ++ include/hw/boards.h | 1 + 3 files changed, 135 insertions(+), 29 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 19c8c3a..22a39b4 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -45,6 +45,7 @@ #include "qemu/error-report.h" #include "hw/pci-host/gpex.h" #include "hw/arm/virt-acpi-build.h" +#include "linux/kvm.h" /* For KVM_DEV_TYPE_ARM_VGIC_V{2|3} */ /* Number of external interrupt lines to configure the GIC with */ #define NUM_IRQS 128 @@ -58,7 +59,7 @@ #define GIC_FDT_IRQ_FLAGS_LEVEL_LO 8 #define GIC_FDT_IRQ_PPI_CPU_START 8 -#define GIC_FDT_IRQ_PPI_CPU_WIDTH 8 +#define GIC_FDT_IRQ_PPI_CPU_WIDTH 24 typedef struct VirtBoardInfo { struct arm_boot_info bootinfo; @@ -69,6 +70,7 @@ typedef struct VirtBoardInfo { void *fdt; int fdt_size; uint32_t clock_phandle; + const char *class_name; } VirtBoardInfo; typedef struct { @@ -82,6 +84,7 @@ typedef struct { } VirtMachineState; #define TYPE_VIRT_MACHINE "virt" +#define TYPE_VIRTV3_MACHINE "virt-v3" #define VIRT_MACHINE(obj) \ OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE) #define VIRT_MACHINE_GET_CLASS(obj) \ @@ -103,20 +106,24 @@ typedef struct { */ static const MemMapEntry a15memmap[] = { /* Space up to 0x8000000 is reserved for a boot ROM */ - [VIRT_FLASH] = { 0, 0x08000000 }, - [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, + [VIRT_FLASH] = { 0, 0x08000000 }, + [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ - [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, - [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, - [VIRT_UART] = { 0x09000000, 0x00001000 }, - [VIRT_RTC] = { 0x09010000, 0x00001000 }, - [VIRT_FW_CFG] = { 0x09020000, 0x0000000a }, - [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, + [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, + [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, + /* On v3 VIRT_GIC_DIST_SPI takes place of VIRT_GIC_CPU */ + [VIRT_ITS_CONTROL] = { 0x08020000, 0x00010000 }, + [VIRT_ITS_TRANSLATION] = { 0x08030000, 0x00010000 }, + [VIRT_LPI] = { 0x08040000, 0x00800000 }, + [VIRT_UART] = { 0x09000000, 0x00001000 }, + [VIRT_RTC] = { 0x09010000, 0x00001000 }, + [VIRT_FW_CFG] = { 0x09020000, 0x0000000a }, + [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ - [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, - [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, - [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, - [VIRT_MEM] = { 0x40000000, 30ULL * 1024 * 1024 * 1024 }, + [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, + [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, + [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, + [VIRT_MEM] = { 0x40000000, 30ULL * 1024 * 1024 * 1024 }, }; static const int a15irqmap[] = { @@ -131,16 +138,25 @@ static VirtBoardInfo machines[] = { .cpu_model = "cortex-a15", .memmap = a15memmap, .irqmap = a15irqmap, + .class_name = TYPE_ARM_CPU, + }, + { + .cpu_model = "cortex-a53", + .memmap = a15memmap, + .irqmap = a15irqmap, + .class_name = TYPE_AARCH64_CPU, }, { .cpu_model = "cortex-a57", .memmap = a15memmap, .irqmap = a15irqmap, + .class_name = TYPE_AARCH64_CPU, }, { .cpu_model = "host", .memmap = a15memmap, .irqmap = a15irqmap, + .class_name = TYPE_ARM_CPU, }, }; @@ -209,7 +225,6 @@ static void fdt_add_psci_node(const VirtBoardInfo *vbi) if (armcpu->psci_version == 2) { const char comp[] = "arm,psci-0.2\0arm,psci"; qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); - cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; @@ -222,7 +237,6 @@ static void fdt_add_psci_node(const VirtBoardInfo *vbi) } } else { qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); - cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; @@ -249,10 +263,13 @@ static void fdt_add_timer_nodes(const VirtBoardInfo *vbi) * they are edge-triggered. */ ARMCPU *armcpu; + uint32_t max; uint32_t irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; + /* Argument is 32 bit but 8 bits are reserved for flags */ + max = (vbi->smp_cpus >= 24) ? 24 : vbi->smp_cpus; irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, - GIC_FDT_IRQ_PPI_CPU_WIDTH, (1 << vbi->smp_cpus) - 1); + GIC_FDT_IRQ_PPI_CPU_WIDTH, (1 << max) - 1); qemu_fdt_add_subnode(vbi->fdt, "/timer"); @@ -276,6 +293,18 @@ static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi) { int cpu; + /* + * From Documentation/devicetree/bindings/arm/cpus.txt + * On ARM v8 64-bit systems value should be set to 2, + * that corresponds to the MPIDR_EL1 register size. + * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs + * in the system, #address-cells can be set to 1, since + * MPIDR_EL1[63:32] bits are not used for CPUs + * identification. + * + * Now GIC500 doesn't support affinities 2 & 3 so currently + * #address-cells can stay 1 until future GIC + */ qemu_fdt_add_subnode(vbi->fdt, "/cpus"); qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#address-cells", 0x1); qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#size-cells", 0x0); @@ -303,7 +332,7 @@ static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi) } } -static uint32_t fdt_add_gic_node(const VirtBoardInfo *vbi) +static uint32_t fdt_add_gic_node(const VirtBoardInfo *vbi, int type) { uint32_t gic_phandle; @@ -311,35 +340,65 @@ static uint32_t fdt_add_gic_node(const VirtBoardInfo *vbi) qemu_fdt_setprop_cell(vbi->fdt, "/", "interrupt-parent", gic_phandle); qemu_fdt_add_subnode(vbi->fdt, "/intc"); - /* 'cortex-a15-gic' means 'GIC v2' */ - qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible", - "arm,cortex-a15-gic"); qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#interrupt-cells", 3); qemu_fdt_setprop(vbi->fdt, "/intc", "interrupt-controller", NULL, 0); - qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg", + if (type == KVM_DEV_TYPE_ARM_VGIC_V3) { + qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible", + "arm,gic-v3"); + qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg", + 2, vbi->memmap[VIRT_GIC_DIST].base, + 2, vbi->memmap[VIRT_GIC_DIST].size, +#if 0 /* Currently no need for SPI & ITS */ + 2, vbi->memmap[VIRT_GIC_DIST_SPI].base, + 2, vbi->memmap[VIRT_GIC_DIST_SPI].size, + 2, vbi->memmap[VIRT_ITS_CONTROL].base, + 2, vbi->memmap[VIRT_ITS_CONTROL].size, + 2, vbi->memmap[VIRT_ITS_TRANSLATION].base, + 2, vbi->memmap[VIRT_ITS_TRANSLATION].size, +#endif + 2, vbi->memmap[VIRT_LPI].base, + 2, vbi->memmap[VIRT_LPI].size); + } else { + /* 'cortex-a15-gic' means 'GIC v2' */ + qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible", + "arm,cortex-a15-gic"); + qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg", 2, vbi->memmap[VIRT_GIC_DIST].base, 2, vbi->memmap[VIRT_GIC_DIST].size, 2, vbi->memmap[VIRT_GIC_CPU].base, 2, vbi->memmap[VIRT_GIC_CPU].size); + } qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", gic_phandle); return gic_phandle; } -static uint32_t create_gic(const VirtBoardInfo *vbi, qemu_irq *pic) +static uint32_t create_gic(const VirtBoardInfo *vbi, qemu_irq *pic, int type) { /* We create a standalone GIC v2 */ DeviceState *gicdev; SysBusDevice *gicbusdev; - const char *gictype = "arm_gic"; + const char *gictype; int i; - if (kvm_irqchip_in_kernel()) { + if (type == KVM_DEV_TYPE_ARM_VGIC_V3) { + gictype = "arm_gicv3"; + } else if (kvm_irqchip_in_kernel()) { gictype = "kvm-arm-gic"; + } else { + gictype = "arm_gic"; } gicdev = qdev_create(NULL, gictype); - qdev_prop_set_uint32(gicdev, "revision", 2); + + for (i = 0; i < vbi->smp_cpus; i++) { + CPUState *cpu = qemu_get_cpu(i); + CPUARMState *env = cpu->env_ptr; + env->nvic = gicdev; + } + + qdev_prop_set_uint32(gicdev, "revision", + type == KVM_DEV_TYPE_ARM_VGIC_V3 ? 3 : 2); qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); /* Note that the num-irq property counts both internal and external * interrupts; there are always 32 of the former (mandated by GIC spec). @@ -349,6 +408,11 @@ static uint32_t create_gic(const VirtBoardInfo *vbi, qemu_irq *pic) gicbusdev = SYS_BUS_DEVICE(gicdev); sysbus_mmio_map(gicbusdev, 0, vbi->memmap[VIRT_GIC_DIST].base); sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_CPU].base); + if (type == KVM_DEV_TYPE_ARM_VGIC_V3) { + sysbus_mmio_map(gicbusdev, 2, vbi->memmap[VIRT_ITS_CONTROL].base); + sysbus_mmio_map(gicbusdev, 3, vbi->memmap[VIRT_ITS_TRANSLATION].base); + sysbus_mmio_map(gicbusdev, 4, vbi->memmap[VIRT_LPI].base); + } /* Wire the outputs from each CPU's generic timer to the * appropriate GIC PPI inputs, and the GIC's IRQ output to @@ -375,7 +439,7 @@ static uint32_t create_gic(const VirtBoardInfo *vbi, qemu_irq *pic) pic[i] = qdev_get_gpio_in(gicdev, i); } - return fdt_add_gic_node(vbi); + return fdt_add_gic_node(vbi, type); } static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic) @@ -748,7 +812,7 @@ static void machvirt_init(MachineState *machine) create_fdt(vbi); for (n = 0; n < smp_cpus; n++) { - ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); + ObjectClass *oc = cpu_class_by_name(vbi->class_name, cpustr[0]); CPUClass *cc = CPU_CLASS(oc); Object *cpuobj; Error *err = NULL; @@ -798,7 +862,7 @@ static void machvirt_init(MachineState *machine) create_flash(vbi); - gic_phandle = create_gic(vbi, pic); + gic_phandle = create_gic(vbi, pic, machine->kernel_irqchip_type); create_uart(vbi, pic); @@ -848,7 +912,7 @@ static void virt_set_secure(Object *obj, bool value, Error **errp) vms->secure = value; } -static void virt_instance_init(Object *obj) +static void virt_instance_init_common(Object *obj) { VirtMachineState *vms = VIRT_MACHINE(obj); @@ -862,6 +926,14 @@ static void virt_instance_init(Object *obj) NULL); } +static void virt_instance_init(Object *obj) +{ + MachineState *ms = MACHINE(obj); + + ms->kernel_irqchip_type = KVM_DEV_TYPE_ARM_VGIC_V2; + virt_instance_init_common(obj); +} + static void virt_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -881,9 +953,38 @@ static const TypeInfo machvirt_info = { .class_init = virt_class_init, }; +static void virtv3_instance_init(Object *obj) +{ + MachineState *ms = MACHINE(obj); + + ms->kernel_irqchip_type = KVM_DEV_TYPE_ARM_VGIC_V3; + virt_instance_init_common(obj); +} + +static void virtv3_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + + mc->name = TYPE_VIRTV3_MACHINE; + mc->desc = "ARM Virtual Machine with GICv3", + mc->init = machvirt_init; + /* With gic3 full implementation (with bitops) rase the lmit to 128 */ + mc->max_cpus = 64; +} + +static const TypeInfo machvirtv3_info = { + .name = TYPE_VIRTV3_MACHINE, + .parent = TYPE_VIRT_MACHINE, + .instance_size = sizeof(VirtMachineState), + .instance_init = virtv3_instance_init, + .class_size = sizeof(VirtMachineClass), + .class_init = virtv3_class_init, +}; + static void machvirt_machine_init(void) { type_register_static(&machvirt_info); + type_register_static(&machvirtv3_info); } machine_init(machvirt_machine_init); diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index ceec8b3..6554630 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -45,6 +45,10 @@ enum { VIRT_CPUPERIPHS, VIRT_GIC_DIST, VIRT_GIC_CPU, + VIRT_GIC_DIST_SPI = VIRT_GIC_CPU, + VIRT_ITS_CONTROL, + VIRT_ITS_TRANSLATION, + VIRT_LPI, VIRT_UART, VIRT_MMIO, VIRT_RTC, diff --git a/include/hw/boards.h b/include/hw/boards.h index ff79797..0734317 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -125,6 +125,7 @@ struct MachineState { char *accel; bool kernel_irqchip_allowed; bool kernel_irqchip_required; + int kernel_irqchip_type; int kvm_shadow_mem; char *dtb; char *dumpdtb;