From patchwork Fri May 29 13:10:18 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 477872 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 27574140F8C for ; Fri, 29 May 2015 23:26:45 +1000 (AEST) Received: from localhost ([::1]:35901 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyKJ9-0000Us-1a for incoming@patchwork.ozlabs.org; Fri, 29 May 2015 09:26:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46348) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyK40-0003xc-5p for qemu-devel@nongnu.org; Fri, 29 May 2015 09:11:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YyK3x-0003bS-Ba for qemu-devel@nongnu.org; Fri, 29 May 2015 09:11:03 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34304) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyK3x-0003US-5A for qemu-devel@nongnu.org; Fri, 29 May 2015 09:11:01 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1YyK3h-0005mU-PR for qemu-devel@nongnu.org; Fri, 29 May 2015 14:10:45 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 29 May 2015 14:10:18 +0100 Message-Id: <1432905045-22138-13-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1432905045-22138-1-git-send-email-peter.maydell@linaro.org> References: <1432905045-22138-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 12/39] target-arm: Move TB flags down to fill gap X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Deleting the now-unused ARM_TBFLAG_CPACR_FPEN left a gap in the bit usage; move the following ARM_TBFLAG_XSCALE_CPAR and ARM_TBFLAG_NS_SHIFT down 3 bits to fill the gap. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- target-arm/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index bf37c49..21b5b8e 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1761,13 +1761,13 @@ static inline bool arm_singlestep_active(CPUARMState *env) /* We store the bottom two bits of the CPAR as TB flags and handle * checks on the other bits at runtime */ -#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 20 +#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) /* Indicates whether cp register reads and writes by guest code should access * the secure or nonsecure bank of banked registers; note that this is not * the same thing as the current security state of the processor! */ -#define ARM_TBFLAG_NS_SHIFT 22 +#define ARM_TBFLAG_NS_SHIFT 19 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) /* Bit usage when in AArch64 state: currently we have no A64 specific bits */