From patchwork Fri May 29 11:01:09 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 477801 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 993D9140129 for ; Fri, 29 May 2015 21:01:31 +1000 (AEST) Received: from localhost ([::1]:35042 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyI2b-00023s-HE for incoming@patchwork.ozlabs.org; Fri, 29 May 2015 07:01:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49515) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyI22-000155-Df for qemu-devel@nongnu.org; Fri, 29 May 2015 07:00:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YyI1w-0001ZG-9K for qemu-devel@nongnu.org; Fri, 29 May 2015 07:00:54 -0400 Received: from mail-lb0-f179.google.com ([209.85.217.179]:33529) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyI1v-0001Z1-NU for qemu-devel@nongnu.org; Fri, 29 May 2015 07:00:47 -0400 Received: by lbcue7 with SMTP id ue7so46016905lbc.0 for ; Fri, 29 May 2015 04:00:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MTLGGDS4oTO4qNYoDGoi389QuHZo+vVWadAEnaCReoA=; b=CMi/ezImQ8PvARDlkLvTqLhXVA0yngpRvvEU7ZrXAZOCzZ68HfelPxvrPBxQhksgq1 Bf7UAeDQDWpOmpLujsjBv0N0249sMRa0H8SAj93xyYsW53mS4OL9UQw9xvPdbGhANrCr 5MJvODb6/0mhTh1jY+6c1hzAsDr6WBCUyF+mazjlK61NF5p98p2q6rYVps4HXu3RsjCY Q+HwzS8xNxFFNwLqRwnQXVMiRhfOKixldHPLCFV9M8wWR2foa24M9UqDz6KwmOXfA6Dz u7H/qv8awyY62orZlidS73MYKZFlM8Ve/iT2UviSXHzSGAv/HZpiiUokdhgJENUmdwxe jltw== X-Gm-Message-State: ALoCoQkr5g7tKBNyo2IPL4zdjC/SfYLEN4h1xTgx+3hFmDC2lIs/Vt//wjOeIldho3lpsfeWQ0Xd X-Received: by 10.112.213.108 with SMTP id nr12mr7468766lbc.42.1432897247001; Fri, 29 May 2015 04:00:47 -0700 (PDT) Received: from localhost.localdomain (188-178-240-98-static.dk.customer.tdc.net. [188.178.240.98]) by mx.google.com with ESMTPSA id zf3sm1319671lbb.2.2015.05.29.04.00.45 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 29 May 2015 04:00:46 -0700 (PDT) From: Christoffer Dall To: qemu-devel@nongnu.org Date: Fri, 29 May 2015 13:01:09 +0200 Message-Id: <1432897270-7780-4-git-send-email-christoffer.dall@linaro.org> X-Mailer: git-send-email 2.1.2.330.g565301e.dirty In-Reply-To: <1432897270-7780-1-git-send-email-christoffer.dall@linaro.org> References: <1432897270-7780-1-git-send-email-christoffer.dall@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.217.179 Cc: Christoffer Dall , kvmarm@lists.cs.columbia.edu, shankerd@codeaurora.org, eric.auger@linaro.org Subject: [Qemu-devel] [PATCH v4 3/4] target-arm: Extend the gic node properties X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In preparation for adding the GICv2m which requires address specifiers and is a subnode of the gic, we extend the gic DT definition to specify the #address-cells and #size-cells properties and add an empty ranges property properties of the DT node, since this is required to add the v2m node as a child of the gic node. Note that we must also expand the irq-map to reference the gic with the right address-cells as a consequence of this change. Reviewed-by: Eric Auger Suggested-by: Shanker Donthineni Signed-off-by: Christoffer Dall --- Changes since v3: - Rewrote patch and changed authorship and tags accordingly - Fixed spelling in commit message Changes since v2: - New separate patch factoring out changes to existing code for eased bisectability in case we broke something - The above fixes the issue with non-MSI compatible guests. hw/arm/virt.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index e5235ef..387dac8 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -317,6 +317,9 @@ static void fdt_add_gic_node(VirtBoardInfo *vbi) 2, vbi->memmap[VIRT_GIC_DIST].size, 2, vbi->memmap[VIRT_GIC_CPU].base, 2, vbi->memmap[VIRT_GIC_CPU].size); + qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#address-cells", 0x2); + qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#size-cells", 0x2); + qemu_fdt_setprop(vbi->fdt, "/intc", "ranges", NULL, 0); qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", vbi->gic_phandle); } @@ -585,7 +588,7 @@ static void create_pcie_irq_map(const VirtBoardInfo *vbi, uint32_t gic_phandle, int first_irq, const char *nodename) { int devfn, pin; - uint32_t full_irq_map[4 * 4 * 8] = { 0 }; + uint32_t full_irq_map[4 * 4 * 10] = { 0 }; uint32_t *irq_map = full_irq_map; for (devfn = 0; devfn <= 0x18; devfn += 0x8) { @@ -598,13 +601,13 @@ static void create_pcie_irq_map(const VirtBoardInfo *vbi, uint32_t gic_phandle, uint32_t map[] = { devfn << 8, 0, 0, /* devfn */ pin + 1, /* PCI pin */ - gic_phandle, irq_type, irq_nr, irq_level }; /* GIC irq */ + gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ /* Convert map to big endian */ - for (i = 0; i < 8; i++) { + for (i = 0; i < 10; i++) { irq_map[i] = cpu_to_be32(map[i]); } - irq_map += 8; + irq_map += 10; } }