diff mbox

[v3,08/15] target-arm: Add TLBI_ALLE1{IS}

Message ID 1432881807-18164-9-git-send-email-edgar.iglesias@gmail.com
State New
Headers show

Commit Message

Edgar E. Iglesias May 29, 2015, 6:43 a.m. UTC 
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target-arm/helper.c | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Peter Maydell June 1, 2015, 3:32 p.m. UTC | #1 
On 29 May 2015 at 07:43, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
>  target-arm/helper.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 193750b..826df50 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2368,6 +2368,14 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
>        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
>        .access = PL1_W, .type = ARM_CP_NOP },
>      /* TLBI operations */
> +    { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
> +      .access = PL2_W, .type = ARM_CP_NO_RAW,
> +      .writefn = tlbiall_write },
> +    { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
> +      .access = PL2_W, .type = ARM_CP_NO_RAW,
> +      .writefn = tlbiall_write },

We should maybe consider implementing support for "only
flush TLB entries for this mmu_idx" in cputlb.c at some
point. This is OK for now, though.

-- PMM
diff mbox

Patch

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 193750b..826df50 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2368,6 +2368,14 @@  static const ARMCPRegInfo v8_cp_reginfo[] = {
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
       .access = PL1_W, .type = ARM_CP_NOP },
     /* TLBI operations */
+    { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
+      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .writefn = tlbiall_write },
+    { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
+      .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
+      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .writefn = tlbiall_write },
     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
       .access = PL1_W, .type = ARM_CP_NO_RAW,