From patchwork Sun May 24 23:47:27 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 476033 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8FC7A1402B4 for ; Mon, 25 May 2015 09:52:13 +1000 (AEST) Received: from localhost ([::1]:41227 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ywfgh-0002Z5-RR for incoming@patchwork.ozlabs.org; Sun, 24 May 2015 19:52:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58331) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YwfcM-00039O-MQ for qemu-devel@nongnu.org; Sun, 24 May 2015 19:47:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YwfcJ-00081K-CN for qemu-devel@nongnu.org; Sun, 24 May 2015 19:47:42 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:101::1]:40633) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YwfcJ-00080C-4Z for qemu-devel@nongnu.org; Sun, 24 May 2015 19:47:39 -0400 Received: from weber.rr44.fr ([2001:470:d4ed:0:7e05:7ff:fe0d:f152]) by hall.aurel32.net with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.84) (envelope-from ) id 1YwfcG-0006oF-NT; Mon, 25 May 2015 01:47:36 +0200 Received: from aurel32 by weber.rr44.fr with local (Exim 4.85) (envelope-from ) id 1YwfcF-0005tI-Ql; Mon, 25 May 2015 01:47:35 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Mon, 25 May 2015 01:47:27 +0200 Message-Id: <1432511251-22515-7-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1432511251-22515-1-git-send-email-aurelien@aurel32.net> References: <1432511251-22515-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:bc8:30d7:101::1 Cc: Alexander Graf , Aurelien Jarno , Richard Henderson Subject: [Qemu-devel] [PATCH 06/10] target-s390x: improve facilities list X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We currently use an hardcoded value for the STFL instruction. Move that to a still hardcoded value but computed from bit values. This is more maintainable and can be reused for the STFLE instruction. Cc: Alexander Graf Cc: Richard Henderson Signed-off-by: Aurelien Jarno --- target-s390x/cpu.h | 66 ++++++++++++++++++++++++++++++++++++++++++++++++ target-s390x/translate.c | 4 +-- 2 files changed, 67 insertions(+), 3 deletions(-) diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h index 99773e0..8bda2e0 100644 --- a/target-s390x/cpu.h +++ b/target-s390x/cpu.h @@ -165,6 +165,72 @@ typedef struct CPUS390XState { #include "cpu-qom.h" #include +/* Facilities list */ +static const uint64_t facilities_dw[] = { + (1ULL << 63) | /* b 0: z/Architecture new instructions added to ESA/390 */ + (1ULL << 62) | /* b 1: z/Architecture architectural */ + (0ULL << 61) | /* b 2: z/Architecture architectural active */ + (0ULL << 60) | /* b 3: IDTE */ + (0ULL << 59) | /* b 4: IDTE selective clearing when segtab invalidated */ + (0ULL << 58) | /* b 5: IDTE selective clearing when regtab invalidated */ + (0ULL << 57) | /* b 6: ASN-and-LX-reuse facility */ + (0ULL << 56) | /* b 7: Store-facility-list-extended facility */ + (0ULL << 55) | /* b 8: Enhanced-DAT facility */ + (0ULL << 54) | /* b 9: Sense-running-status facility */ + (0ULL << 53) | /* b10: Conditional-SSKE facility */ + (0ULL << 52) | /* b11: Configuration-topology facility */ + (0ULL << 51) | /* b12: IBM internal use */ + (0ULL << 50) | /* b13: IPTE-Range facility */ + (0ULL << 49) | /* b14: Nonquiescing key-setting facility */ + (0ULL << 48) | /* b15: IBM internal use */ + (0ULL << 47) | /* b16: Extended-translation facility 2 */ + (0ULL << 46) | /* b17: Message-security assist */ + (0ULL << 45) | /* b18: Long-displacement facility */ + (0ULL << 44) | /* b19: High performance long-displacement facility */ + (0ULL << 43) | /* b20: HFP-multiply-and-add/subtract facility */ + (0ULL << 42) | /* b21: Extended-immediate facility */ + (0ULL << 41) | /* b22: Extended-translation facility 3 */ + (0ULL << 40) | /* b23: HFP-unnormalized-extension facility */ + (0ULL << 39) | /* b24: ETF2-enhancement facility */ + (0ULL << 38) | /* b25: Store-clock-fast facility */ + (0ULL << 37) | /* b26: Parsing-enhancement facility */ + (0ULL << 36) | /* b27: Move-with-optional-specifications facility */ + (0ULL << 35) | /* b28: TOD-clock-steering facility */ + (0ULL << 33) | /* b30: ETF3-enhancement facility */ + (0ULL << 32) | /* b31: Extract-CPU-time facility */ + (0ULL << 31) | /* b32: Compare-and-swap-and-store facility */ + (0ULL << 30) | /* b33: Compare-and-swap-and-store facility 2 */ + (0ULL << 29) | /* b34: General-instructions-extension facility */ + (0ULL << 28) | /* b35: Execute-extensions facility */ + (0ULL << 27) | /* b36: Enhanced-monitor facility */ + (0ULL << 26) | /* b37: Floating-point extension facility */ + (0ULL << 24) | /* b39: IBM internal use */ + (0ULL << 23) | /* b40: Set-program-parameters facility */ + (0ULL << 22) | /* b41: Floating-point-support-enhancement facilities */ + (0ULL << 21) | /* b42: DFP facility */ + (0ULL << 20) | /* b43: High performance DFP facility */ + (0ULL << 19) | /* b44: PFPO instruction */ + (0ULL << 18) | /* b45: Fast-BCR-serialization facility */ + (0ULL << 17) | /* b46: IBM internal use */ + (0ULL << 16) | /* b47: CMPSC-enhancement facility */ + (0ULL << 15) | /* b48: DFP zoned-conversion facility */ + (0ULL << 14) | /* b49: Execution-hint, load-and-trap facility */ + (0ULL << 13) | /* b50: Transactional-execution facility */ + (0ULL << 12) | /* b51: Local-TLB-clearing facility */ + (0ULL << 11) | /* b52: interlocked-access facility 2 */ + (0ULL << 1) | /* b62: IBM internal use */ + (0ULL << 0) /* b63: IBM internal use */ +, + (0ULL << 61) | /* b66: Reset-reference-bits-multiple facility */ + (0ULL << 60) | /* b67: CPU-measurement counter facility */ + (0ULL << 59) | /* b68: CPU-measurement sampling facility */ + (0ULL << 54) | /* b73: Transactional-execution facility in zArch */ + (0ULL << 52) | /* b75: Access-exception-fetch/store-indication facility */ + (0ULL << 51) | /* b76: Message-security-assist-extension-3 facility */ + (0ULL << 50) | /* b77: Message-security-assist-extension-4 facility */ + (0ULL << 49) /* b78: Enhanced-DAT facility 2 */ +}; + /* distinguish between 24 bit and 31 bit addressing */ #define HIGH_ORDER_BIT 0x80000000 diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 745195f..542da53 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -3373,10 +3373,8 @@ static ExitStatus op_spt(DisasContext *s, DisasOps *o) static ExitStatus op_stfl(DisasContext *s, DisasOps *o) { TCGv_i64 f, a; - /* We really ought to have more complete indication of facilities - that we implement. Address this when STFLE is implemented. */ check_privileged(s); - f = tcg_const_i64(0xc0000000); + f = tcg_const_i64(facilities_dw[0] >> 32); a = tcg_const_i64(200); tcg_gen_qemu_st32(f, a, get_mem_index(s)); tcg_temp_free_i64(f);