From patchwork Fri May 22 15:06:03 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Koppelmann X-Patchwork-Id: 475651 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 0FACF14029C for ; Sat, 23 May 2015 01:12:26 +1000 (AEST) Received: from localhost ([::1]:34452 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YvocZ-0000k3-Ub for incoming@patchwork.ozlabs.org; Fri, 22 May 2015 11:12:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37035) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YvoWj-0007k8-Sq for qemu-devel@nongnu.org; Fri, 22 May 2015 11:06:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YvoWh-0007Tt-4I for qemu-devel@nongnu.org; Fri, 22 May 2015 11:06:21 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:33094) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YvoWg-0007Sx-Ta for qemu-devel@nongnu.org; Fri, 22 May 2015 11:06:19 -0400 From: Bastian Koppelmann To: qemu-devel@nongnu.org Date: Fri, 22 May 2015 17:06:03 +0200 Message-Id: <1432307168-10401-6-git-send-email-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.4.1 In-Reply-To: <1432307168-10401-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1432307168-10401-1-git-send-email-kbastian@mail.uni-paderborn.de> X-IMT-Spam-Score: 0.0 () X-PMX-Version: 6.2.0.2453472, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2015.5.22.145717 X-IMT-Authenticated-Sender: uid=kbastian,ou=People,o=upb,c=de X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PULL 05/10] target-tricore: add SWAPMSK instructions of the v1.6.1 ISA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Those instruction were introduced in the new Aurix platform. Signed-off-by: Bastian Koppelmann Reviewed-by: Richard Henderson --- target-tricore/translate.c | 39 +++++++++++++++++++++++++++++++++++++++ target-tricore/tricore-opcodes.h | 5 +++++ 2 files changed, 44 insertions(+) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 06d183b..b2e25e7 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -333,6 +333,25 @@ static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea) tcg_temp_free(temp2); } +static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea) +{ + TCGv temp = tcg_temp_new(); + TCGv temp2 = tcg_temp_new(); + TCGv temp3 = tcg_temp_new(); + + tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); + tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]); + tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]); + tcg_gen_or_tl(temp2, temp2, temp3); + tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); + tcg_gen_mov_tl(cpu_gpr_d[reg], temp); + + tcg_temp_free(temp); + tcg_temp_free(temp2); + tcg_temp_free(temp3); +} + + /* We generate loads and store to core special function register (csfr) through the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3 makros R, A and E, which allow read-only, all and endinit protected access. @@ -5072,6 +5091,18 @@ static void decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState *env, tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); break; + case OPC2_32_BO_SWAPMSK_W_SHORTOFF: + tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); + gen_swapmsk(ctx, r1, temp); + break; + case OPC2_32_BO_SWAPMSK_W_POSTINC: + gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); + tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); + break; + case OPC2_32_BO_SWAPMSK_W_PREINC: + tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); + gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); + break; } tcg_temp_free(temp); tcg_temp_free(temp2); @@ -5123,6 +5154,14 @@ static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState *env, gen_cmpswap(ctx, r1, temp2); gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); break; + case OPC2_32_BO_SWAPMSK_W_BR: + gen_swapmsk(ctx, r1, temp2); + gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); + break; + case OPC2_32_BO_SWAPMSK_W_CIRC: + gen_swapmsk(ctx, r1, temp2); + gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); + break; } tcg_temp_free(temp); diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index 95837aa..7ad6df9 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -766,6 +766,9 @@ enum { OPC2_32_BO_CMPSWAP_W_SHORTOFF = 0x23, OPC2_32_BO_CMPSWAP_W_POSTINC = 0x03, OPC2_32_BO_CMPSWAP_W_PREINC = 0x13, + OPC2_32_BO_SWAPMSK_W_SHORTOFF = 0x22, + OPC2_32_BO_SWAPMSK_W_POSTINC = 0x02, + OPC2_32_BO_SWAPMSK_W_PREINC = 0x12, }; /*OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR */ enum { @@ -775,6 +778,8 @@ enum { OPC2_32_BO_SWAP_W_CIRC = 0x10, OPC2_32_BO_CMPSWAP_W_BR = 0x03, OPC2_32_BO_CMPSWAP_W_CIRC = 0x13, + OPC2_32_BO_SWAPMSK_W_BR = 0x02, + OPC2_32_BO_SWAPMSK_W_CIRC = 0x12, }; /* * BRC Format