From patchwork Mon May 18 19:15:05 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 473577 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 7C12114029C for ; Tue, 19 May 2015 05:22:45 +1000 (AEST) Received: from localhost ([::1]:42695 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YuQcd-0005vn-Bt for incoming@patchwork.ozlabs.org; Mon, 18 May 2015 15:22:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42495) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YuQVq-0001dO-Au for qemu-devel@nongnu.org; Mon, 18 May 2015 15:15:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YuQVo-0000AM-II for qemu-devel@nongnu.org; Mon, 18 May 2015 15:15:41 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34173) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YuQVo-0008QT-1r for qemu-devel@nongnu.org; Mon, 18 May 2015 15:15:40 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1YuQVV-0007uL-Av for qemu-devel@nongnu.org; Mon, 18 May 2015 20:15:21 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 18 May 2015 20:15:05 +0100 Message-Id: <1431976521-30352-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1431976521-30352-1-git-send-email-peter.maydell@linaro.org> References: <1431976521-30352-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 05/21] arm: xlnx-zynqmp: Connect CPU Timers to GIC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter Crosthwaite Connect the GPIO outputs from the individual CPUs for the timers to the GIC. Tested-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Signed-off-by: Peter Crosthwaite Message-id: a7866a4f0c903c91fa3034210b4d2879aa4bfcb9.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- hw/arm/xlnx-zynqmp.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index d4c5309..f98e9f7 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -16,10 +16,14 @@ */ #include "hw/arm/xlnx-zynqmp.h" +#include "hw/intc/arm_gic_common.h" #include "exec/address-spaces.h" #define GIC_NUM_SPI_INTR 160 +#define ARM_PHYS_TIMER_PPI 30 +#define ARM_VIRT_TIMER_PPI 27 + #define GIC_BASE_ADDR 0xf9000000 #define GIC_DIST_ADDR 0xf9010000 #define GIC_CPU_ADDR 0xf9020000 @@ -34,6 +38,11 @@ static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { { .region_index = 1, .address = GIC_CPU_ADDR, }, }; +static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) +{ + return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; +} + static void xlnx_zynqmp_init(Object *obj) { XlnxZynqMPState *s = XLNX_ZYNQMP(obj); @@ -86,6 +95,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) } for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) { + qemu_irq irq; + object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC, "psci-conduit", &error_abort); if (i > 0) { @@ -109,6 +120,12 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); + irq = qdev_get_gpio_in(DEVICE(&s->gic), + arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); + qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 0, irq); + irq = qdev_get_gpio_in(DEVICE(&s->gic), + arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); + qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 1, irq); } }