From patchwork Mon May 11 13:40:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 470819 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D971C14016A for ; Mon, 11 May 2015 23:47:48 +1000 (AEST) Received: from localhost ([::1]:37491 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yro3f-0006WK-06 for incoming@patchwork.ozlabs.org; Mon, 11 May 2015 09:47:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42408) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yrnwu-0002O1-OI for qemu-devel@nongnu.org; Mon, 11 May 2015 09:40:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yrnwt-0000fX-L5 for qemu-devel@nongnu.org; Mon, 11 May 2015 09:40:48 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34140) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yrnws-0000d0-Pg for qemu-devel@nongnu.org; Mon, 11 May 2015 09:40:47 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Yrnwl-0005fa-As for qemu-devel@nongnu.org; Mon, 11 May 2015 14:40:39 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 11 May 2015 14:40:35 +0100 Message-Id: <1431351638-21705-17-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1431351638-21705-1-git-send-email-peter.maydell@linaro.org> References: <1431351638-21705-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 16/19] hw/intc/arm_gic: Add grouping support to gic_update() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add support to gic_update() for determining the current IRQ and FIQ status when interrupt grouping is supported. This simply requires that instead of always raising IRQ we check the group of the highest priority pending interrupt and the GICC_CTLR.FIQEn bit to see whether we should raise IRQ or FIQ. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Message-id: 1430502643-25909-15-git-send-email-peter.maydell@linaro.org --- hw/intc/arm_gic.c | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 6abdb14..c1d2e70 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -60,7 +60,7 @@ void gic_update(GICState *s) int best_irq; int best_prio; int irq; - int level; + int irq_level, fiq_level; int cpu; int cm; @@ -70,6 +70,7 @@ void gic_update(GICState *s) if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) { qemu_irq_lower(s->parent_irq[cpu]); + qemu_irq_lower(s->parent_fiq[cpu]); return; } best_prio = 0x100; @@ -83,15 +84,31 @@ void gic_update(GICState *s) } } } - level = 0; + + irq_level = fiq_level = 0; + if (best_prio < s->priority_mask[cpu]) { s->current_pending[cpu] = best_irq; if (best_prio < s->running_priority[cpu]) { - DPRINTF("Raised pending IRQ %d (cpu %d)\n", best_irq, cpu); - level = 1; + int group = GIC_TEST_GROUP(best_irq, cm); + + if (extract32(s->ctlr, group, 1) && + extract32(s->cpu_ctlr[cpu], group, 1)) { + if (group == 0 && s->cpu_ctlr[cpu] & GICC_CTLR_FIQ_EN) { + DPRINTF("Raised pending FIQ %d (cpu %d)\n", + best_irq, cpu); + fiq_level = 1; + } else { + DPRINTF("Raised pending IRQ %d (cpu %d)\n", + best_irq, cpu); + irq_level = 1; + } + } } } - qemu_set_irq(s->parent_irq[cpu], level); + + qemu_set_irq(s->parent_irq[cpu], irq_level); + qemu_set_irq(s->parent_fiq[cpu], fiq_level); } }