From patchwork Thu Apr 30 18:14:27 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christopher Covington X-Patchwork-Id: 466677 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 0363414031A for ; Fri, 1 May 2015 04:17:22 +1000 (AEST) Received: from localhost ([::1]:45267 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ynt1U-0006vl-5f for incoming@patchwork.ozlabs.org; Thu, 30 Apr 2015 14:17:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38509) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YnszV-0003fO-UL for qemu-devel@nongnu.org; Thu, 30 Apr 2015 14:15:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YnszQ-0002Bn-VB for qemu-devel@nongnu.org; Thu, 30 Apr 2015 14:15:17 -0400 Received: from mail-pa0-f41.google.com ([209.85.220.41]:35530) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YnszQ-0002Bj-QT for qemu-devel@nongnu.org; Thu, 30 Apr 2015 14:15:12 -0400 Received: by pabtp1 with SMTP id tp1so67028659pab.2 for ; Thu, 30 Apr 2015 11:15:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Xe9WlG4KSCy3zTzXuH0iqLsG5xtYKAF3nPcFaI6YrIo=; b=epfW7iRGLUVg0TNbyPSFw4zNQdv6Zws7fYyREEXbTW3WK/imw0fmLmpvOFQUQDqHI0 VQw9ikuQ/ZtBR/gFcq17R/wxqbN9/joF2XueV/4J/t3zChWGgYlYglo2UV9PQTsqd3PT 6paSle5+Olk/AXkJ87bfTAEZSpVIipxkYCE+CkgqHXuuQYjHHZGaO7qi7/PWEdTIKJI+ vXMPnaiRKi4Lu0SZiIaJg441ts3ze7HPZjJvBqppzxU4VIY7aDXRLuKPBu9sr4J8rJRq 1JdNpQt23uGcLTLvyLAfFtShb/VxG41f6YSh7FHRs6OK8s+3bfnCoPBp0foAkonBtoYv 15Cg== X-Gm-Message-State: ALoCoQl8n1hXPQHnaaqPq7MAZb0dg2wZCC/VKv7AbVrnuB6modeZdHKzevP5yU3K/oh0O/Eoc2tA X-Received: by 10.66.252.3 with SMTP id zo3mr10486701pac.26.1430417712398; Thu, 30 Apr 2015 11:15:12 -0700 (PDT) Received: from covaro.wlan.qualcomm.com (rrcs-67-52-130-29.west.biz.rr.com. [67.52.130.29]) by mx.google.com with ESMTPSA id y2sm2799818pbt.46.2015.04.30.11.15.09 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 30 Apr 2015 11:15:11 -0700 (PDT) From: Christopher Covington To: peter.maydell@linaro.org, qemu-devel@nongnu.org Date: Thu, 30 Apr 2015 14:14:27 -0400 Message-Id: <1430417667-4245-5-git-send-email-christopher.covington@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1430417667-4245-1-git-send-email-christopher.covington@linaro.org> References: <1430417667-4245-1-git-send-email-christopher.covington@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.41 Cc: Christopher Covington Subject: [Qemu-devel] [RFC 5/5] arm: Simplify cycle counter X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Present a system with an instructions per cycle of exactly one. This makes it less likely a user will mistake the cycle counter values as meaningful and makes calculations involving cycles trivial while preserving the necessary property of the cycle counter register as monotonically increasing. Signed-off-by: Christopher Covington --- target-arm/helper.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 3e6fb0b..a027a19 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -648,8 +648,7 @@ void pmccntr_sync(CPUARMState *env) { uint64_t temp_ticks; - temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL), - get_ticks_per_sec(), 1000000); + temp_ticks = cpu_get_icount_raw(); if (env->cp15.c9_pmcr & PMCRD) { /* Increment once every 64 processor clock cycles */ @@ -687,8 +686,7 @@ static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) return env->cp15.c15_ccnt; } - total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL), - get_ticks_per_sec(), 1000000); + total_ticks = cpu_get_icount_raw(); if (env->cp15.c9_pmcr & PMCRD) { /* Increment once every 64 processor clock cycles */ @@ -708,8 +706,7 @@ static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, return; } - total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL), - get_ticks_per_sec(), 1000000); + total_ticks = cpu_get_icount_raw(); if (env->cp15.c9_pmcr & PMCRD) { /* Increment once every 64 processor clock cycles */