From patchwork Mon Apr 20 09:19:16 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gerd Hoffmann X-Patchwork-Id: 462758 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 50638140213 for ; Mon, 20 Apr 2015 19:20:21 +1000 (AEST) Received: from localhost ([::1]:52467 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yk7sI-0000DG-Vv for incoming@patchwork.ozlabs.org; Mon, 20 Apr 2015 05:20:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53218) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yk7ri-0007Wm-Lo for qemu-devel@nongnu.org; Mon, 20 Apr 2015 05:19:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yk7re-0001f8-Iy for qemu-devel@nongnu.org; Mon, 20 Apr 2015 05:19:42 -0400 Received: from mx1.redhat.com ([209.132.183.28]:54465) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yk7re-0001ee-9r for qemu-devel@nongnu.org; Mon, 20 Apr 2015 05:19:38 -0400 Received: from int-mx13.intmail.prod.int.phx2.redhat.com (int-mx13.intmail.prod.int.phx2.redhat.com [10.5.11.26]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id t3K9Jbil026663 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Mon, 20 Apr 2015 05:19:37 -0400 Received: from nilsson.home.kraxel.org (ovpn-116-48.ams2.redhat.com [10.36.116.48]) by int-mx13.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id t3K9Jab9031039; Mon, 20 Apr 2015 05:19:37 -0400 Received: by nilsson.home.kraxel.org (Postfix, from userid 500) id 9F82B8085E; Mon, 20 Apr 2015 11:19:35 +0200 (CEST) From: Gerd Hoffmann To: qemu-devel@nongnu.org Date: Mon, 20 Apr 2015 11:19:16 +0200 Message-Id: <1429521560-2743-2-git-send-email-kraxel@redhat.com> In-Reply-To: <1429521560-2743-1-git-send-email-kraxel@redhat.com> References: <1429521560-2743-1-git-send-email-kraxel@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.26 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: pbonzini@redhat.com, lersek@redhat.com, Gerd Hoffmann , mst@redhat.com Subject: [Qemu-devel] [PATCH 2/6] add SMRAM+ESMRAMC wmask X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Gerd Hoffmann Reviewed-by: Michael S. Tsirkin --- hw/pci-host/q35.c | 2 ++ include/hw/pci-host/q35.h | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 9735db2..7093cc3 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -352,6 +352,8 @@ static void mch_reset(DeviceState *qdev) d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; + d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; + d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; mch_update(mch); } diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index 9704ccd..82452c5 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -141,6 +141,11 @@ typedef struct Q35PCIHost { #define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000 #define MCH_HOST_BRIDGE_SMRAM_DEFAULT \ MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG +#define MCH_HOST_BRIDGE_SMRAM_WMASK \ + (MCH_HOST_BRIDGE_SMRAM_D_OPEN | \ + MCH_HOST_BRIDGE_SMRAM_D_CLS | \ + MCH_HOST_BRIDGE_SMRAM_D_LCK | \ + MCH_HOST_BRIDGE_SMRAM_G_SMRAME) #define MCH_HOST_BRIDGE_ESMRAMC 0x9e #define MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 7)) @@ -157,6 +162,10 @@ typedef struct Q35PCIHost { (MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE | \ MCH_HOST_BRIDGE_ESMRAMC_SM_L1 | \ MCH_HOST_BRIDGE_ESMRAMC_SM_L2) +#define MCH_HOST_BRIDGE_ESMRAMC_WMASK \ + (MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME | \ + MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK | \ + MCH_HOST_BRIDGE_ESMRAMC_T_EN) /* D1:F0 PCIE* port*/ #define MCH_PCIE_DEV 1