From patchwork Mon Mar 23 01:17:45 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tiejun Chen X-Patchwork-Id: 453276 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id CE42D14011D for ; Mon, 23 Mar 2015 12:20:31 +1100 (AEDT) Received: from localhost ([::1]:53177 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YZr2b-00059S-PG for incoming@patchwork.ozlabs.org; Sun, 22 Mar 2015 21:20:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59327) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YZr1Y-0003kX-S0 for qemu-devel@nongnu.org; Sun, 22 Mar 2015 21:19:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YZr1T-0002Vr-3V for qemu-devel@nongnu.org; Sun, 22 Mar 2015 21:19:24 -0400 Received: from mga09.intel.com ([134.134.136.24]:5256) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YZr1S-0002Vc-On for qemu-devel@nongnu.org; Sun, 22 Mar 2015 21:19:19 -0400 Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP; 22 Mar 2015 18:19:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,448,1422950400"; d="scan'208";a="544693751" Received: from tchen0-linux.bj.intel.com ([10.238.154.91]) by orsmga003.jf.intel.com with ESMTP; 22 Mar 2015 18:19:00 -0700 From: Tiejun Chen To: ian.campbell@citrix.com, wei.liu2@citrix.com, Ian.Jackson@eu.citrix.com, stefano.stabellini@citrix.com Date: Mon, 23 Mar 2015 09:17:45 +0800 Message-Id: <1427073466-16956-2-git-send-email-tiejun.chen@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1427073466-16956-1-git-send-email-tiejun.chen@intel.com> References: <1427073466-16956-1-git-send-email-tiejun.chen@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.24 Cc: qemu-devel@nongnu.org, xen-devel@lists.xen.org Subject: [Qemu-devel] [v3][PATCH 1/2] libxl: introduce libxl__is_igd_vga_passthru X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org While working with qemu, IGD is a specific device in the case of pass through so we need to identify that to handle more later. Here we define a table to record all IGD types currently we can support. Also we need to introduce two helper functions to get vendor and device ids to lookup that table. Signed-off-by: Tiejun Chen Acked-by: Ian Campbell --- tools/libxl/libxl_internal.h | 2 + tools/libxl/libxl_pci.c | 124 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 126 insertions(+) diff --git a/tools/libxl/libxl_internal.h b/tools/libxl/libxl_internal.h index 934465a..c97c62d 100644 --- a/tools/libxl/libxl_internal.h +++ b/tools/libxl/libxl_internal.h @@ -1176,6 +1176,8 @@ _hidden int libxl__device_pci_add(libxl__gc *gc, uint32_t domid, libxl_device_pc _hidden int libxl__create_pci_backend(libxl__gc *gc, uint32_t domid, libxl_device_pci *pcidev, int num); _hidden int libxl__device_pci_destroy_all(libxl__gc *gc, uint32_t domid); +_hidden bool libxl__is_igd_vga_passthru(libxl__gc *gc, + const libxl_domain_config *d_config); /*----- xswait: wait for a xenstore node to be suitable -----*/ diff --git a/tools/libxl/libxl_pci.c b/tools/libxl/libxl_pci.c index f3ae132..9a534cc 100644 --- a/tools/libxl/libxl_pci.c +++ b/tools/libxl/libxl_pci.c @@ -491,6 +491,130 @@ static int sysfs_dev_unbind(libxl__gc *gc, libxl_device_pci *pcidev, return 0; } +static uint16_t sysfs_dev_get_vendor(libxl__gc *gc, libxl_device_pci *pcidev) +{ + char *pci_device_vendor_path = + GCSPRINTF(SYSFS_PCI_DEV"/"PCI_BDF"/vendor", + pcidev->domain, pcidev->bus, pcidev->dev, pcidev->func); + uint16_t read_items; + uint16_t pci_device_vendor; + + FILE *f = fopen(pci_device_vendor_path, "r"); + if (!f) { + LOGE(ERROR, + "pci device "PCI_BDF" does not have vendor attribute", + pcidev->domain, pcidev->bus, pcidev->dev, pcidev->func); + return 0xffff; + } + read_items = fscanf(f, "0x%hx\n", &pci_device_vendor); + fclose(f); + if (read_items != 1) { + LOGE(ERROR, + "cannot read vendor of pci device "PCI_BDF, + pcidev->domain, pcidev->bus, pcidev->dev, pcidev->func); + return 0xffff; + } + + return pci_device_vendor; +} + +static uint16_t sysfs_dev_get_device(libxl__gc *gc, libxl_device_pci *pcidev) +{ + char *pci_device_device_path = + GCSPRINTF(SYSFS_PCI_DEV"/"PCI_BDF"/device", + pcidev->domain, pcidev->bus, pcidev->dev, pcidev->func); + uint16_t read_items; + uint16_t pci_device_device; + + FILE *f = fopen(pci_device_device_path, "r"); + if (!f) { + LOGE(ERROR, + "pci device "PCI_BDF" does not have device attribute", + pcidev->domain, pcidev->bus, pcidev->dev, pcidev->func); + return 0xffff; + } + read_items = fscanf(f, "0x%hx\n", &pci_device_device); + fclose(f); + if (read_items != 1) { + LOGE(ERROR, + "cannot read device of pci device "PCI_BDF, + pcidev->domain, pcidev->bus, pcidev->dev, pcidev->func); + return 0xffff; + } + + return pci_device_device; +} + +typedef struct { + uint16_t vendor; + uint16_t device; +} pci_info; + +static const pci_info fixup_ids[] = { + /* Intel HSW Classic */ + {0x8086, 0x0402}, /* HSWGT1D, HSWD_w7 */ + {0x8086, 0x0406}, /* HSWGT1M, HSWM_w7 */ + {0x8086, 0x0412}, /* HSWGT2D, HSWD_w7 */ + {0x8086, 0x0416}, /* HSWGT2M, HSWM_w7 */ + {0x8086, 0x041E}, /* HSWGT15D, HSWD_w7 */ + /* Intel HSW ULT */ + {0x8086, 0x0A06}, /* HSWGT1UT, HSWM_w7 */ + {0x8086, 0x0A16}, /* HSWGT2UT, HSWM_w7 */ + {0x8086, 0x0A26}, /* HSWGT3UT, HSWM_w7 */ + {0x8086, 0x0A2E}, /* HSWGT3UT28W, HSWM_w7 */ + {0x8086, 0x0A1E}, /* HSWGT2UX, HSWM_w7 */ + {0x8086, 0x0A0E}, /* HSWGT1ULX, HSWM_w7 */ + /* Intel HSW CRW */ + {0x8086, 0x0D26}, /* HSWGT3CW, HSWM_w7 */ + {0x8086, 0x0D22}, /* HSWGT3CWDT, HSWD_w7 */ + /* Intel HSW Server */ + {0x8086, 0x041A}, /* HSWSVGT2, HSWD_w7 */ + /* Intel HSW SRVR */ + {0x8086, 0x040A}, /* HSWSVGT1, HSWD_w7 */ + /* Intel BSW */ + {0x8086, 0x1606}, /* BDWULTGT1, BDWM_w7 */ + {0x8086, 0x1616}, /* BDWULTGT2, BDWM_w7 */ + {0x8086, 0x1626}, /* BDWULTGT3, BDWM_w7 */ + {0x8086, 0x160E}, /* BDWULXGT1, BDWM_w7 */ + {0x8086, 0x161E}, /* BDWULXGT2, BDWM_w7 */ + {0x8086, 0x1602}, /* BDWHALOGT1, BDWM_w7 */ + {0x8086, 0x1612}, /* BDWHALOGT2, BDWM_w7 */ + {0x8086, 0x1622}, /* BDWHALOGT3, BDWM_w7 */ + {0x8086, 0x162B}, /* BDWHALO28W, BDWM_w7 */ + {0x8086, 0x162A}, /* BDWGT3WRKS, BDWM_w7 */ + {0x8086, 0x162D}, /* BDWGT3SRVR, BDWM_w7 */ +}; + +/* + * Some devices may need some ways to work well. Here like IGD, + * we have to pass a specific option to qemu. + */ +bool libxl__is_igd_vga_passthru(libxl__gc *gc, + const libxl_domain_config *d_config) +{ + unsigned int i, j, num = ARRAY_SIZE(fixup_ids); + uint16_t vendor, device, pt_vendor, pt_device; + + for (i = 0 ; i < d_config->num_pcidevs ; i++) { + libxl_device_pci *pcidev = &d_config->pcidevs[i]; + pt_vendor = sysfs_dev_get_vendor(gc, pcidev); + pt_device = sysfs_dev_get_device(gc, pcidev); + + if (pt_vendor == 0xffff || pt_device == 0xffff) + continue; + + for (j = 0 ; j < num ; j++) { + vendor = fixup_ids[j].vendor; + device = fixup_ids[j].device; + + if (pt_vendor == vendor && pt_device == device) + return true; + } + } + + return false; +} + /* * A brief comment about slots. I don't know what slots are for; however, * I have by experimentation determined: