From patchwork Wed Feb 25 16:02:39 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 443482 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 38EC4140083 for ; Thu, 26 Feb 2015 03:07:09 +1100 (AEDT) Received: from localhost ([::1]:54792 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YQeUN-0001du-BH for incoming@patchwork.ozlabs.org; Wed, 25 Feb 2015 11:07:07 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47445) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YQeQG-0002ZA-5Q for qemu-devel@nongnu.org; Wed, 25 Feb 2015 11:02:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YQeQF-0006us-GI for qemu-devel@nongnu.org; Wed, 25 Feb 2015 11:02:52 -0500 Received: from static.88-198-71-155.clients.your-server.de ([88.198.71.155]:47158 helo=socrates.bennee.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YQeQF-0006uk-BB for qemu-devel@nongnu.org; Wed, 25 Feb 2015 11:02:51 -0500 Received: from localhost ([127.0.0.1] helo=zen.linaroharston) by socrates.bennee.com with esmtp (Exim 4.80) (envelope-from ) id 1YQfOG-0007hX-M5; Wed, 25 Feb 2015 18:04:52 +0100 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Wed, 25 Feb 2015 16:02:39 +0000 Message-Id: <1424880159-29348-8-git-send-email-alex.bennee@linaro.org> X-Mailer: git-send-email 2.3.0 In-Reply-To: <1424880159-29348-1-git-send-email-alex.bennee@linaro.org> References: <1424880159-29348-1-git-send-email-alex.bennee@linaro.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 127.0.0.1 X-SA-Exim-Mail-From: alex.bennee@linaro.org X-SA-Exim-Scanned: No (on socrates.bennee.com); SAEximRunCond expanded to false X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 88.198.71.155 Cc: Peter Maydell , kvm@vger.kernel.org, marc.zyngier@arm.com, linux-arm-kernel@lists.infradead.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH 6/6] target-arm/cpu.h: document why env->spsr exists X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org I was getting very confused about the duplication of state. Perhaps we should just get rid of env->spsr and use helpers that understand the banking? Signed-off-by: Alex Bennée Reviewed-by: Greg Bellows diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 11845a6..d7fd13f 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -155,6 +155,11 @@ typedef struct CPUARMState { This contains all the other bits. Use cpsr_{read,write} to access the whole CPSR. */ uint32_t uncached_cpsr; + /* The spsr is a alias for spsr_elN where N is the current + * exception level. It is provided for here so the TCG msr/mrs + * implementation can access one register. Care needs to be taken + * to ensure the banked_spsr[] is also updated. + */ uint32_t spsr; /* Banked registers. */