From patchwork Tue Feb 17 10:10:04 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 440549 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id AEC641401AB for ; Tue, 17 Feb 2015 21:14:18 +1100 (AEDT) Received: from localhost ([::1]:44576 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YNfAW-0003Lj-Kk for incoming@patchwork.ozlabs.org; Tue, 17 Feb 2015 05:14:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34467) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YNf7x-00079I-6P for qemu-devel@nongnu.org; Tue, 17 Feb 2015 05:11:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YNf7r-0000sV-2j for qemu-devel@nongnu.org; Tue, 17 Feb 2015 05:11:37 -0500 Received: from szxga01-in.huawei.com ([119.145.14.64]:9641) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YNf7q-0000qa-EC for qemu-devel@nongnu.org; Tue, 17 Feb 2015 05:11:30 -0500 Received: from 172.24.2.119 (EHLO szxeml426-hub.china.huawei.com) ([172.24.2.119]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CJQ38100; Tue, 17 Feb 2015 18:11:14 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml426-hub.china.huawei.com (10.82.67.181) with Microsoft SMTP Server id 14.3.158.1; Tue, 17 Feb 2015 18:10:57 +0800 From: Shannon Zhao To: , , , , , , , , , Date: Tue, 17 Feb 2015 18:10:04 +0800 Message-ID: <1424167806-8372-6-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1424167806-8372-1-git-send-email-zhaoshenglong@huawei.com> References: <1424167806-8372-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] X-Received-From: 119.145.14.64 Cc: wanghaibin.wang@huawei.com, hangaohuai@huawei.com, peter.huangpeng@huawei.com Subject: [Qemu-devel] [RFC PATCH 5/7] target-arm/cpu: Add apic_id property for ARMCPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add apic_id property for ARMCPU. It can be used for cpu hotplug. Signed-off-by: Shannon Zhao --- target-arm/cpu-qom.h | 1 + target-arm/cpu.c | 77 ++++++++++++++++++++++++++++++++++++++++++++++++++ target-arm/cpu.h | 2 + 3 files changed, 80 insertions(+), 0 deletions(-) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index ed5a644..d4560e2 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -59,6 +59,7 @@ typedef struct ARMCPU { /*< public >*/ CPUARMState env; + uint32_t apic_id; /* Coprocessor information */ GHashTable *cp_regs; diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 285947f..9202b07 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -23,12 +23,17 @@ #include "qemu-common.h" #include "hw/qdev-properties.h" #include "qapi/qmp/qerror.h" +#include "qapi-visit.h" +#include "qapi/visitor.h" +#include "hw/acpi/topology.h" + #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" #endif #include "hw/arm/arm.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" +#include "sysemu/cpus.h" #include "kvm_arm.h" static void arm_cpu_set_pc(CPUState *cs, vaddr value) @@ -332,6 +337,65 @@ static inline void unset_feature(CPUARMState *env, int feature) env->features &= ~(1ULL << feature); } +static void arm_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque, + const char *name, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + int64_t value = cpu->apic_id; + + visit_type_int(v, &value, name, errp); +} + +static void arm_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque, + const char *name, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + DeviceState *dev = DEVICE(obj); + const int64_t min = 0; + const int64_t max = UINT32_MAX; + Error *error = NULL; + int64_t value; + + if (dev->realized) { + error_setg(errp, "Attempt to set property '%s' on '%s' after " + "it was realized", name, object_get_typename(obj)); + return; + } + + visit_type_int(v, &value, name, &error); + if (error) { + error_propagate(errp, error); + return; + } + if (value < min || value > max) { + error_setg(errp, "Property %s.%s doesn't take value %" PRId64 + " (minimum: %" PRId64 ", maximum: %" PRId64 ")" , + object_get_typename(obj), name, value, min, max); + return; + } + + if ((value != cpu->apic_id) && cpu_exists(value)) { + error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value); + return; + } + cpu->apic_id = value; +} + +/* Calculates initial APIC ID for a specific CPU index + * + * Currently we need to be able to calculate the APIC ID from the CPU index + * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have + * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of + * all CPUs up to max_cpus. + */ +uint32_t arm_cpu_apic_id_from_index(unsigned int cpu_index) +{ + uint32_t correct_id; + + correct_id = apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); + return correct_id; +} + static void arm_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); @@ -343,6 +407,11 @@ static void arm_cpu_initfn(Object *obj) cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); + object_property_add(obj, "apic-id", "int", + arm_cpuid_get_apic_id, + arm_cpuid_set_apic_id, NULL, NULL, NULL); + + cpu->apic_id = arm_cpu_apic_id_from_index(cs->cpu_index); #ifndef CONFIG_USER_ONLY /* Our inbound IRQ and FIQ lines */ if (kvm_enabled()) { @@ -379,6 +448,13 @@ static void arm_cpu_initfn(Object *obj) } } +static int64_t arm_cpu_get_arch_id(CPUState *cs) +{ + ARMCPU *cpu = ARM_CPU(cs); + + return cpu->apic_id; +} + static Property arm_cpu_reset_cbar_property = DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); @@ -1183,6 +1259,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) cc->set_pc = arm_cpu_set_pc; cc->gdb_read_register = arm_cpu_gdb_read_register; cc->gdb_write_register = arm_cpu_gdb_write_register; + cc->get_arch_id = arm_cpu_get_arch_id; #ifdef CONFIG_USER_ONLY cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; #else diff --git a/target-arm/cpu.h b/target-arm/cpu.h index cd7a9e8..9e60972 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1819,4 +1819,6 @@ enum { QEMU_PSCI_CONDUIT_HVC = 2, }; +uint32_t arm_cpu_apic_id_from_index(unsigned int cpu_index); + #endif