From patchwork Tue Feb 3 21:46:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Snow X-Patchwork-Id: 436056 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8185214012E for ; Wed, 4 Feb 2015 08:55:26 +1100 (AEDT) Received: from localhost ([::1]:33470 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YIlRM-00087Y-QR for incoming@patchwork.ozlabs.org; Tue, 03 Feb 2015 16:55:24 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45844) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YIlJ9-0001re-I6 for qemu-devel@nongnu.org; Tue, 03 Feb 2015 16:47:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YIlJ3-0002dZ-4v for qemu-devel@nongnu.org; Tue, 03 Feb 2015 16:46:55 -0500 Received: from mx1.redhat.com ([209.132.183.28]:53021) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YIlJ2-0002dF-UL for qemu-devel@nongnu.org; Tue, 03 Feb 2015 16:46:49 -0500 Received: from int-mx13.intmail.prod.int.phx2.redhat.com (int-mx13.intmail.prod.int.phx2.redhat.com [10.5.11.26]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id t13LklX8000716 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Tue, 3 Feb 2015 16:46:48 -0500 Received: from scv.usersys.redhat.com ([10.18.17.161]) by int-mx13.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id t13LkfQl002721; Tue, 3 Feb 2015 16:46:46 -0500 From: John Snow To: qemu-devel@nongnu.org Date: Tue, 3 Feb 2015 16:46:26 -0500 Message-Id: <1422999999-25868-7-git-send-email-jsnow@redhat.com> In-Reply-To: <1422999999-25868-1-git-send-email-jsnow@redhat.com> References: <1422999999-25868-1-git-send-email-jsnow@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.26 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: famz@redhat.com, mst@redhat.com, armbru@redhat.com, stefanha@redhat.com, pbonzini@redhat.com, John Snow Subject: [Qemu-devel] [PATCH v2 06/19] libqos/ahci: Add ahci_port_check_interrupts helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org A helper that compares a given port's current interrupts and checks them against a supplied list of expected interrupt bits, and throws an error if they do not match. The helper then resets the requested interrupts on this port, and asserts that the interrupt register is now empty. Signed-off-by: John Snow Reviewed-by: Paolo Bonzini --- tests/ahci-test.c | 13 ++----------- tests/libqos/ahci.c | 14 ++++++++++++++ tests/libqos/ahci.h | 2 ++ 3 files changed, 18 insertions(+), 11 deletions(-) diff --git a/tests/ahci-test.c b/tests/ahci-test.c index a3e8f12..32b6be3 100644 --- a/tests/ahci-test.c +++ b/tests/ahci-test.c @@ -747,19 +747,10 @@ static void ahci_test_identify(AHCIQState *ahci) while (BITSET(ahci_px_rreg(ahci, i, AHCI_PX_TFD), AHCI_PX_TFD_STS_BSY)) { usleep(50); } + /* Check registers for post-command consistency */ ahci_port_check_error(ahci, i); - - /* Check for expected interrupts */ - reg = ahci_px_rreg(ahci, i, AHCI_PX_IS); - ASSERT_BIT_SET(reg, AHCI_PX_IS_DHRS); - ASSERT_BIT_SET(reg, AHCI_PX_IS_PSS); /* BUG: we expect AHCI_PX_IS_DPS to be set. */ - ASSERT_BIT_CLEAR(reg, AHCI_PX_IS_DPS); - - /* Clear expected interrupts and assert all interrupts now cleared. */ - ahci_px_wreg(ahci, i, AHCI_PX_IS, - AHCI_PX_IS_DHRS | AHCI_PX_IS_PSS | AHCI_PX_IS_DPS); - g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_IS), ==, 0); + ahci_port_check_interrupts(ahci, i, AHCI_PX_IS_DHRS | AHCI_PX_IS_PSS); /* Investigate the CMD, assert that we read 512 bytes */ ahci_get_command_header(ahci, i, cx, &cmd); diff --git a/tests/libqos/ahci.c b/tests/libqos/ahci.c index ef2b50e..d6e0c0b 100644 --- a/tests/libqos/ahci.c +++ b/tests/libqos/ahci.c @@ -333,6 +333,20 @@ void ahci_port_check_error(AHCIQState *ahci, uint8_t px) ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR); } +void ahci_port_check_interrupts(AHCIQState *ahci, uint8_t px, + uint32_t intr_mask) +{ + uint32_t reg; + + /* Check for expected interrupts */ + reg = ahci_px_rreg(ahci, px, AHCI_PX_IS); + ASSERT_BIT_SET(reg, intr_mask); + + /* Clear expected interrupts and assert all interrupts now cleared. */ + ahci_px_wreg(ahci, px, AHCI_PX_IS, intr_mask); + g_assert_cmphex(ahci_px_rreg(ahci, px, AHCI_PX_IS), ==, 0); +} + /* Get the #cx'th command of port #px. */ void ahci_get_command_header(AHCIQState *ahci, uint8_t px, uint8_t cx, AHCICommandHeader *cmd) diff --git a/tests/libqos/ahci.h b/tests/libqos/ahci.h index b384cbc..4b6696a 100644 --- a/tests/libqos/ahci.h +++ b/tests/libqos/ahci.h @@ -434,6 +434,8 @@ void ahci_hba_enable(AHCIQState *ahci); unsigned ahci_port_select(AHCIQState *ahci); void ahci_port_clear(AHCIQState *ahci, uint8_t px); void ahci_port_check_error(AHCIQState *ahci, uint8_t px); +void ahci_port_check_interrupts(AHCIQState *ahci, uint8_t px, + uint32_t intr_mask); void ahci_get_command_header(AHCIQState *ahci, uint8_t px, uint8_t cx, AHCICommandHeader *cmd); void ahci_set_command_header(AHCIQState *ahci, uint8_t px,