From patchwork Wed Jan 21 18:49:52 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 431581 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id F2268140284 for ; Thu, 22 Jan 2015 05:51:08 +1100 (AEDT) Received: from localhost ([::1]:49751 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YE0Mt-0007al-6e for incoming@patchwork.ozlabs.org; Wed, 21 Jan 2015 13:51:07 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50425) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YE0M0-0006Br-J3 for qemu-devel@nongnu.org; Wed, 21 Jan 2015 13:50:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YE0Lx-0001Lq-Bl for qemu-devel@nongnu.org; Wed, 21 Jan 2015 13:50:12 -0500 Received: from mail-pa0-f47.google.com ([209.85.220.47]:54317) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YE0Lx-0001Ku-3S for qemu-devel@nongnu.org; Wed, 21 Jan 2015 13:50:09 -0500 Received: by mail-pa0-f47.google.com with SMTP id lj1so10305036pab.6 for ; Wed, 21 Jan 2015 10:50:08 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pW7Ev3BZt3DPuWPB3r/zCJ3TtoFjoDX3BuD/Eb8qpoI=; b=TrBxKQ/21/8cemMINxVluVbfJgdfepjGHBLDNWuQe28sC2zLHYxx/T3T5U9YJXzuDn YNMwE+1ZFqfPRNI1FIbBtx3Ple1UkPU5WlYTVdhua1evYf1Gch7a6k7T+R10kpnUCpgl AfkQ5tEPShjen+4ekN8Uem1cX45K1iIBJge1+3XOLj2OrTPtyK37V92G3vR5IqVYsE5U bsj1Z/qT3ui7jfMxPXO6xVR2OeU5HV8RQEC0CGg93itYGUpgS2fty6/wrgPDAs21rhZ7 srOMgbQP3w1bYT1g+f3YjUcqPAC3tq8sTMgrvtHL4bRKdd6wIe+UVO3smPjdywZql6xr Vnjw== X-Gm-Message-State: ALoCoQm1eGQeCCQyCNEuUHT/COkqrHjBws3NCajvXxZPZdaZr2H2Pnnqq2BDB5hJH81WZoJuTmA+ X-Received: by 10.68.191.101 with SMTP id gx5mr65466796pbc.108.1421866208464; Wed, 21 Jan 2015 10:50:08 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id zk9sm7047429pac.1.2015.01.21.10.50.06 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 21 Jan 2015 10:50:07 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, christoffer.dall@linaro.org Date: Wed, 21 Jan 2015 12:49:52 -0600 Message-Id: <1421866193-24941-4-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1421866193-24941-1-git-send-email-greg.bellows@linaro.org> References: <1421866193-24941-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.47 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH v2 3/4] target-arm: Add 32/64-bit register sync X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add AArch32 to AArch64 register sychronization functions. Replace manual register synchronization with new functions in aarch64_cpu_do_interrupt() and HELPER(exception_return)(). Signed-off-by: Greg Bellows --- target-arm/helper-a64.c | 5 +-- target-arm/internals.h | 89 +++++++++++++++++++++++++++++++++++++++++++++++++ target-arm/op_helper.c | 6 ++-- 3 files changed, 92 insertions(+), 8 deletions(-) diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index 81066ca..2b5a668 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -448,7 +448,6 @@ void aarch64_cpu_do_interrupt(CPUState *cs) unsigned int new_el = arm_excp_target_el(cs, cs->exception_index); target_ulong addr = env->cp15.vbar_el[new_el]; unsigned int new_mode = aarch64_pstate_mode(new_el, true); - int i; if (arm_current_el(env) < new_el) { if (env->aarch64) { @@ -512,9 +511,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs) } env->elr_el[new_el] = env->regs[15]; - for (i = 0; i < 15; i++) { - env->xregs[i] = env->regs[i]; - } + aarch64_sync_32_to_64(env); env->condexec_bits = 0; } diff --git a/target-arm/internals.h b/target-arm/internals.h index bb171a7..626ea7d 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -128,6 +128,95 @@ static inline void aarch64_restore_sp(CPUARMState *env, int el) } } +static inline void aarch64_sync_32_to_64(CPUARMState *env) +{ + int i; + + /* We can blanket copy R[0:7] to X[0:7] */ + for (i = 0; i < 8; i++) { + env->xregs[i] = env->regs[i]; + } + + /* If we are in USR mode then we just want to complete the above blanket + * copy so we get the accurate register values. If not, then we have to go + * to the saved and banked user regs. + */ + if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) { + for (i = 8; i < 15; i++) { + env->xregs[i] = env->regs[i]; + } + } else { + for (i = 8; i < 13; i++) { + env->xregs[i] = env->usr_regs[i-8]; + } + env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; + env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)]; + } + env->pc = env->regs[15]; + + env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; + env->xregs[16] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; + env->xregs[17] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)]; + env->xregs[18] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; + env->xregs[19] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)]; + env->xregs[20] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; + env->xregs[21] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)]; + env->xregs[22] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; + env->xregs[23] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)]; + + for (i = 0; i < 5; i++) { + env->xregs[24+i] = env->fiq_regs[i]; + } + env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; + env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)]; +} + +static inline void aarch64_sync_64_to_32(CPUARMState *env) +{ + int i; + + /* We can blanket copy R[0:7] to X[0:7] */ + for (i = 0; i < 8; i++) { + env->regs[i] = env->xregs[i]; + } + + /* If we are in USR mode then we want to complete the above blanket + * copy as the XREGs will contain the most recent value. + */ + if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) { + for (i = 8; i < 15; i++) { + env->regs[i] = env->xregs[i]; + } + } + + /* Update the user copies and banked registers so they are also up to + * date. + */ + for (i = 8; i < 13; i++) { + env->usr_regs[i-8] = env->xregs[i]; + } + env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13]; + env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; + + env->regs[15] = env->pc; + + env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15]; + env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; + env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; + env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; + env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; + env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; + env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; + env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; + env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; + + for (i = 0; i < 5; i++) { + env->fiq_regs[i] = env->xregs[24+i]; + } + env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; + env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; +} + static inline void update_spsel(CPUARMState *env, uint32_t imm) { unsigned int cur_el = arm_current_el(env); diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 2bed914..7713022 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -465,7 +465,7 @@ void HELPER(exception_return)(CPUARMState *env) int cur_el = arm_current_el(env); unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el); uint32_t spsr = env->banked_spsr[spsr_idx]; - int new_el, i; + int new_el; aarch64_save_sp(env, cur_el); @@ -491,9 +491,7 @@ void HELPER(exception_return)(CPUARMState *env) if (!arm_singlestep_active(env)) { env->uncached_cpsr &= ~PSTATE_SS; } - for (i = 0; i < 15; i++) { - env->regs[i] = env->xregs[i]; - } + aarch64_sync_64_to_32(env); env->regs[15] = env->elr_el[1] & ~0x1; } else {