diff mbox

[2/2] target-arm : update section number of decoder reference manual

Message ID 1419351903-8693-2-git-send-email-cmchao@gmail.com
State New
Headers show

Commit Message

cmchao Dec. 23, 2014, 4:25 p.m. UTC 
The changes are based on reference manual version, DDI0487A_c,
    and most of them are SIMD related sub-chapter

Signed-off-by: Chih-Min Chao <cmchao@gmail.com>
---
 target-arm/translate-a64.c | 36 ++++++++++++++++++------------------
 1 file changed, 18 insertions(+), 18 deletions(-)
diff mbox

Patch

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 979572a..3d1057f 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1050,7 +1050,7 @@  static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table,
  * of the ARM Architecture Reference Manual (DDI0487A_c)
  */
 
-/* C4.2.7 Unconditional branch (immediate)
+/* C4.2.6 Unconditional branch (immediate)
  *   31  30       26 25                                  0
  * +----+-----------+-------------------------------------+
  * | op | 0 0 1 0 1 |                 imm26               |
@@ -1871,8 +1871,8 @@  static void disas_ld_lit(DisasContext *s, uint32_t insn)
  * C4.3.7 Load/store no-allocate pair (offset)
  *   C6.6.80 LDNP (Load Pair - non-temporal hint)
  *   C6.6.176 STNP (Store Pair - non-temporal hint)
- *   C7.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
- *   C7.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
+ *   C7.3.164 LDNP (Load Pair of SIMD&FP - non-temporal hint)
+ *   C7.3.283 STNP (Store Pair of SIMD&FP - non-temporal hint)
  * C4.3.14 Load/store register pair (offset)
  *   C6.6.81 LDP (Load Pair - non vector)
  *   C6.6.82 LDPSW (Load Pair Signed Word - non vector)
@@ -5076,7 +5076,7 @@  static void do_ext64(DisasContext *s, TCGv_i64 tcg_left, TCGv_i64 tcg_right,
     tcg_temp_free_i64(tcg_tmp);
 }
 
-/* C4.6.1 EXT
+/* C4.6.3 EXT
  *   31  30 29         24 23 22  21 20  16 15  14  11 10  9    5 4    0
  * +---+---+-------------+-----+---+------+---+------+---+------+------+
  * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 |  Rm  | 0 | imm4 | 0 |  Rn  |  Rd  |
@@ -5149,7 +5149,7 @@  static void disas_simd_ext(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(tcg_resh);
 }
 
-/* C4.6.2 TBL/TBX
+/* C4.6.14 TBL/TBX
  *   31  30 29         24 23 22  21 20  16 15  14 13  12  11 10 9    5 4    0
  * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
  * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 |  Rm  | 0 | len | op | 0 0 |  Rn  |  Rd  |
@@ -5217,7 +5217,7 @@  static void disas_simd_tb(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(tcg_resh);
 }
 
-/* C4.6.3 ZIP/UZP/TRN
+/* C4.6.5 ZIP/UZP/TRN
  *   31  30 29         24 23  22  21 20   16 15 14 12 11 10 9    5 4    0
  * +---+---+-------------+------+---+------+---+------------------+------+
  * | 0 | Q | 0 0 1 1 1 0 | size | 0 |  Rm  | 0 | opc | 1 0 |  Rn  |  Rd  |
@@ -5329,7 +5329,7 @@  static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2,
     }
 }
 
-/* C4.6.4 AdvSIMD across lanes
+/* C4.6.1 AdvSIMD across lanes
  *   31  30  29 28       24 23  22 21       17 16    12 11 10 9    5 4    0
  * +---+---+---+-----------+------+-----------+--------+-----+------+------+
  * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 |  Rn  |  Rd  |
@@ -5719,7 +5719,7 @@  static void handle_simd_umov_smov(DisasContext *s, int is_q, int is_signed,
     }
 }
 
-/* C4.6.5 AdvSIMD copy
+/* C4.6.2 AdvSIMD copy
  *   31  30  29  28             21 20  16 15  14  11 10  9    5 4    0
  * +---+---+----+-----------------+------+---+------+---+------+------+
  * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 |  Rn  |  Rd  |
@@ -5771,7 +5771,7 @@  static void disas_simd_copy(DisasContext *s, uint32_t insn)
     }
 }
 
-/* C4.6.6 AdvSIMD modified immediate
+/* C4.6.4 AdvSIMD modified immediate
  *  31  30   29  28                 19 18 16 15   12  11  10  9     5 4    0
  * +---+---+----+---------------------+-----+-------+----+---+-------+------+
  * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh |  Rd  |
@@ -5904,7 +5904,7 @@  static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(tcg_imm);
 }
 
-/* C4.6.7 AdvSIMD scalar copy
+/* C4.6.6 AdvSIMD scalar copy
  *  31 30  29  28             21 20  16 15  14  11 10  9    5 4    0
  * +-----+----+-----------------+------+---+------+---+------+------+
  * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 |  Rn  |  Rd  |
@@ -5927,7 +5927,7 @@  static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn)
     handle_simd_dupes(s, rd, rn, imm5);
 }
 
-/* C4.6.8 AdvSIMD scalar pairwise
+/* C4.6.7 AdvSIMD scalar pairwise
  *  31 30  29 28       24 23  22 21       17 16    12 11 10 9    5 4    0
  * +-----+---+-----------+------+-----------+--------+-----+------+------+
  * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 |  Rn  |  Rd  |
@@ -6653,7 +6653,7 @@  static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
     tcg_temp_free_i32(tcg_rmode);
 }
 
-/* C4.6.9 AdvSIMD scalar shift by immediate
+/* C4.6.8 AdvSIMD scalar shift by immediate
  *  31 30  29 28         23 22  19 18  16 15    11  10 9    5 4    0
  * +-----+---+-------------+------+------+--------+---+------+------+
  * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 |  Rn  |  Rd  |
@@ -6728,7 +6728,7 @@  static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
     }
 }
 
-/* C4.6.10 AdvSIMD scalar three different
+/* C4.6.9 AdvSIMD scalar three different
  *  31 30  29 28       24 23  22  21 20  16 15    12 11 10 9    5 4    0
  * +-----+---+-----------+------+---+------+--------+-----+------+------+
  * | 0 1 | U | 1 1 1 1 0 | size | 1 |  Rm  | opcode | 0 0 |  Rn  |  Rd  |
@@ -7115,7 +7115,7 @@  static void handle_3same_float(DisasContext *s, int size, int elements,
     }
 }
 
-/* C4.6.11 AdvSIMD scalar three same
+/* C4.6.10 AdvSIMD scalar three same
  *  31 30  29 28       24 23  22  21 20  16 15    11  10 9    5 4    0
  * +-----+---+-----------+------+---+------+--------+---+------+------+
  * | 0 1 | U | 1 1 1 1 0 | size | 1 |  Rm  | opcode | 1 |  Rn  |  Rd  |
@@ -7786,7 +7786,7 @@  static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
     }
 }
 
-/* C4.6.12 AdvSIMD scalar two reg misc
+/* C4.6.11 AdvSIMD scalar two reg misc
  *  31 30  29 28       24 23  22 21       17 16    12 11 10 9    5 4    0
  * +-----+---+-----------+------+-----------+--------+-----+------+------+
  * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 |  Rn  |  Rd  |
@@ -8214,7 +8214,7 @@  static void handle_vec_simd_shrn(DisasContext *s, bool is_q,
 }
 
 
-/* C4.6.14 AdvSIMD shift by immediate
+/* C4.6.13 AdvSIMD shift by immediate
  *  31  30   29 28         23 22  19 18  16 15    11  10 9    5 4    0
  * +---+---+---+-------------+------+------+--------+---+------+------+
  * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 |  Rn  |  Rd  |
@@ -8639,7 +8639,7 @@  static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int rm)
     tcg_temp_free_i64(tcg_res);
 }
 
-/* C4.6.15 AdvSIMD three different
+/* C4.6.14 AdvSIMD three different
  *   31  30  29 28       24 23  22  21 20  16 15    12 11 10 9    5 4    0
  * +---+---+---+-----------+------+---+------+--------+-----+------+------+
  * | 0 | Q | U | 0 1 1 1 0 | size | 1 |  Rm  | opcode | 0 0 |  Rn  |  Rd  |
@@ -10157,7 +10157,7 @@  static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
     }
 }
 
-/* C4.6.13 AdvSIMD scalar x indexed element
+/* C4.6.12 AdvSIMD scalar x indexed element
  *  31 30  29 28       24 23  22 21  20  19  16 15 12  11  10 9    5 4    0
  * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
  * | 0 1 | U | 1 1 1 1 1 | size | L | M |  Rm  | opc | H | 0 |  Rn  |  Rd  |