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[PULL,22/30] target-mips: Also apply the CP0.Status mask to MTTC0

Message ID 1418759356-14242-23-git-send-email-leon.alrae@imgtec.com
State New
Headers show

Commit Message

Leon Alrae Dec. 16, 2014, 7:49 p.m. UTC 
From: "Maciej W. Rozycki" <macro@codesourcery.com>

Make CP0.Status writes made with the MTTC0 instruction respect this
register's mask just like all the other places.  Also preserve the
current values of masked out bits.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 target-mips/op_helper.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
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Patch

diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 1267ef2..7e632f6 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -1413,9 +1413,10 @@  void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
+    uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 
-    other->CP0_Status = arg1 & ~0xf1000018;
+    other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
     sync_c0_status(env, other, other_tc);
 }