From patchwork Tue Dec 16 19:49:00 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 422038 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 9D57F1400DD for ; Wed, 17 Dec 2014 06:56:04 +1100 (AEDT) Received: from localhost ([::1]:46519 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y0yDy-00067F-Ri for incoming@patchwork.ozlabs.org; Tue, 16 Dec 2014 14:56:02 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47662) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y0y8O-0004oo-UI for qemu-devel@nongnu.org; Tue, 16 Dec 2014 14:50:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Y0y8I-0002kO-Fb for qemu-devel@nongnu.org; Tue, 16 Dec 2014 14:50:16 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:20263) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y0y8I-0002kG-4z for qemu-devel@nongnu.org; Tue, 16 Dec 2014 14:50:10 -0500 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id B0C04C38A5017; Tue, 16 Dec 2014 19:50:05 +0000 (GMT) Received: from lalrae-linux.kl.imgtec.org (192.168.14.163) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Tue, 16 Dec 2014 19:50:08 +0000 From: Leon Alrae To: Date: Tue, 16 Dec 2014 19:49:00 +0000 Message-ID: <1418759356-14242-15-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1418759356-14242-1-git-send-email-leon.alrae@imgtec.com> References: <1418759356-14242-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.14.163] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: "Maciej W. Rozycki" Subject: [Qemu-devel] [PULL 14/30] target-mips: Correct the handling of writes to CP0.Status for MIPSr6 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Maciej W. Rozycki" Correct these issues with the handling of CP0.Status for MIPSr6: * only ignore the bit pattern of 0b11 on writes to CP0.Status.KSU, that is for processors that do implement Supervisor Mode, let the bit pattern be written to CP0.Status.UM:R0 freely (of course the value written to read-only CP0.Status.R0 will be discarded anyway); this is in accordance to the relevant architecture specification[1], * check the newly written pattern rather than the current contents of CP0.Status for the KSU bits being 0b11, * use meaningful macro names to refer to CP0.Status bits rather than magic numbers. References: [1] "MIPS Architecture For Programmers, Volume III: MIPS64 / microMIPS64 Privileged Resource Architecture", MIPS Technologies, Inc., Document Number: MD00091, Revision 6.00, March 31, 2014, Table 9.45 "Status Register Field Descriptions", pp. 210-211. Signed-off-by: Maciej W. Rozycki Reviewed-by: Leon Alrae Signed-off-by: Leon Alrae --- target-mips/op_helper.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index d25424f..a0cc729 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -1423,10 +1423,12 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) uint32_t mask = env->CP0_Status_rw_bitmask; if (env->insn_flags & ISA_MIPS32R6) { - if (extract32(env->CP0_Status, CP0St_KSU, 2) == 0x3) { + bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3; + + if (has_supervisor && extract32(arg1, CP0St_KSU, 2) == 0x3) { mask &= ~(3 << CP0St_KSU); } - mask &= ~(0x00180000 & arg1); + mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & arg1); } val = arg1 & mask;