From patchwork Mon Dec 15 23:09:49 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 421720 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id BB4C014009B for ; Tue, 16 Dec 2014 10:18:04 +1100 (AEDT) Received: from localhost ([::1]:42383 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y0etu-0008D8-Sn for incoming@patchwork.ozlabs.org; Mon, 15 Dec 2014 18:18:02 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36069) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y0ema-0003pY-Ro for qemu-devel@nongnu.org; Mon, 15 Dec 2014 18:10:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Y0emU-0000i4-DQ for qemu-devel@nongnu.org; Mon, 15 Dec 2014 18:10:28 -0500 Received: from mail-pd0-f178.google.com ([209.85.192.178]:50061) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y0emU-0000hd-8t for qemu-devel@nongnu.org; Mon, 15 Dec 2014 18:10:22 -0500 Received: by mail-pd0-f178.google.com with SMTP id r10so12514196pdi.23 for ; Mon, 15 Dec 2014 15:10:21 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=d5xirxGPsKkAE7w064kYb39tT5Sss42kjTnxDvWGMf8=; b=cBY4lSk4wwdXdWmDtumhEHbih4nN/AWYHQNFrEIlxDu6nhKAS09TWUicQu4FhOod7V WPfcVKdwKQh6Y7RryPbPBS0Cn8JF484UTZ/5GQUUkY3b42p4xr50RLcyLIEKLTbRbQ6E QZ8IqBkbyNCnY0b/VAIxLAWtoMdc49w+8oSaR3Kd/vCqz4nmnMx6hyMoucv6mH0wVoA6 QavCdUPDSI83yxsWjqR62ELCV66irAgpEcaxmjOLaznfVtlzJbqwegv1lxBzlB1s9WBI d1YUV17KHOGQRDP4UmKY/RQZczJlnE191s7sPW/THBx5t50BoGgRzbvKQzN1ZuH27Px2 WG3g== X-Gm-Message-State: ALoCoQkjBhRznxq2zOsPOwcmIMvufpvq4590lApx0Q03xWBC3dnsWOLc1ELveSd7P506w8cJgDBx X-Received: by 10.70.91.176 with SMTP id cf16mr55181659pdb.100.1418685021888; Mon, 15 Dec 2014 15:10:21 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id uq15sm10402467pab.8.2014.12.15.15.10.20 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 15 Dec 2014 15:10:21 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Mon, 15 Dec 2014 17:09:49 -0600 Message-Id: <1418684992-8996-13-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1418684992-8996-1-git-send-email-greg.bellows@linaro.org> References: <1418684992-8996-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.178 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH v4 12/15] target-arm: Set CPU has_el3 prop during virt init X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Adds setting of the CPU has_el3 property based on the virt machine secure state property during initialization. This enables/disables EL3 state during start-up. Changes include adding an additional secure state boolean during virt CPU initialization. Also disables the ARM secure boot by default. Signed-off-by: Greg Bellows --- v1 -> v2 - Changes CPU property name from "secure" to "has_el3" - Change conditional to handle machine state default of secure. The check now checks if the machine secure property has been disabled which causes the CPU EL3 feature to be disabled. - Add setting of arm_boot_info.secure_boot to false v2 -> v3 - Silently ignore error if "has_el3" does not exist - Remove board initialization of secure_boot as it is implied. - Revise secure machine property description v3 -> v4 - Move machine secure property description change to correct patch. --- hw/arm/virt.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 73c68c7..a9e13ca 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -547,6 +547,7 @@ static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) static void machvirt_init(MachineState *machine) { + VirtMachineState *vms = VIRT_MACHINE(machine); qemu_irq pic[NUM_IRQS]; MemoryRegion *sysmem = get_system_memory(); int n; @@ -584,6 +585,10 @@ static void machvirt_init(MachineState *machine) } cpuobj = object_new(object_class_get_name(oc)); + if (!vms->secure) { + object_property_set_bool(cpuobj, false, "has_el3", NULL); + } + object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_HVC, "psci-conduit", NULL);