From patchwork Wed Dec 3 20:06:04 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 417539 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 092501400D5 for ; Thu, 4 Dec 2014 07:14:55 +1100 (AEDT) Received: from localhost ([::1]:43224 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XwGK4-00027d-Ux for incoming@patchwork.ozlabs.org; Wed, 03 Dec 2014 15:14:52 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54099) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XwGC2-0006qZ-7g for qemu-devel@nongnu.org; Wed, 03 Dec 2014 15:06:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XwGBu-0003YK-Sm for qemu-devel@nongnu.org; Wed, 03 Dec 2014 15:06:34 -0500 Received: from mail-ob0-f175.google.com ([209.85.214.175]:56754) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XwGBu-0003YC-Nn for qemu-devel@nongnu.org; Wed, 03 Dec 2014 15:06:26 -0500 Received: by mail-ob0-f175.google.com with SMTP id wp4so1688395obc.34 for ; Wed, 03 Dec 2014 12:06:26 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qyyOvwcs4JSEf2P/okrf5Hs7w460PF5lvBdZnmbf1+4=; b=MxzSXM9lFUqosyR1gdTFu3vu/W6H6Ej0sXmtzPAjNA4qRiWJEjqKWwCHVSt2Qjc/zU sWipdOn9HO3EcuAT2b47DYRxxhCYIcPPwztG44RVZZx73h9atfUpx2HikSLiD/V1TFgD vuYEu3I33jqKmmemyLMlaJaRldGCNiAc2+klXBTullY8GBe7OYUVDqgGl1Ez+KWP9vFg d4l4T+axFjHESQJtL8sa5OcvvynKnxKwScISpr6v8dgVFIlsE2f1Bg4HQKFO6lOIpQyx 83JeM9YGqd1DB59Rf4JWSG6cMPgFFvOYDUMKaelMXddVUU5fkHdHOBaQAVJ2iV1CWNgy cjMw== X-Gm-Message-State: ALoCoQmn7Gbq54IE4JqXqmRSnrwYsDWm5qDDZbbjY+4NFz+jbVtjt3V8+80EIgCLuBDzxUDZL5jE X-Received: by 10.182.213.72 with SMTP id nq8mr4259734obc.11.1417637186425; Wed, 03 Dec 2014 12:06:26 -0800 (PST) Received: from gbellows-linaro.bellowshome.net (99-179-1-128.lightspeed.austtx.sbcglobal.net. [99.179.1.128]) by mx.google.com with ESMTPSA id mq4sm11787321obb.22.2014.12.03.12.06.25 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 03 Dec 2014 12:06:25 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Wed, 3 Dec 2014 14:06:04 -0600 Message-Id: <1417637167-20640-11-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1417637167-20640-1-git-send-email-greg.bellows@linaro.org> References: <1417637167-20640-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.175 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH 10/13] target-arm: Add ARMCPU secure property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Added a "secure" state property to the ARMCPU descriptor. This property indicates whether the ARMCPU is enabled for secure state or not. By default it is disabled at this time. Signed-off-by: Greg Bellows --- target-arm/cpu-qom.h | 2 ++ target-arm/cpu.c | 24 ++++++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index dcfda7d..8dab91b 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -100,6 +100,8 @@ typedef struct ARMCPU { bool start_powered_off; /* CPU currently in PSCI powered-off state */ bool powered_off; + /* CPU secure state enabled */ + bool secure; /* PSCI conduit used to invoke PSCI methods * 0 - disabled, 1 - smc, 2 - hvc diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 01afed2..0e660f9 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -388,6 +388,9 @@ static Property arm_cpu_reset_hivecs_property = static Property arm_cpu_rvbar_property = DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); +static Property arm_cpu_secure_property = + DEFINE_PROP_BOOL("secure", ARMCPU, secure, false); + static void arm_cpu_post_init(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -407,6 +410,14 @@ static void arm_cpu_post_init(Object *obj) qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, &error_abort); } + + if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { + /* Add the secure state CPU property only if EL3 is allowed. This will + * prevent "secure" from existing on non EL3 enabled machines. + */ + qdev_property_add_static(DEVICE(obj), &arm_cpu_secure_property, + &error_abort); + } } static void arm_cpu_finalizefn(Object *obj) @@ -476,6 +487,19 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) cpu->reset_sctlr |= (1 << 13); } + if (arm_feature(env, ARM_FEATURE_V6) && !cpu->secure) { + /* The security extension and ID_PFR1 only apply to ARMv6 and up. IF + * this is the case and secure state has not been enabled then we + * disable the security extension feature. + */ + unset_feature(env, ARM_FEATURE_EL3); + + /* Disable the security extension feature bits in the processor feature + * register as well. This is id_pfr1[7:4]. + */ + cpu->id_pfr1 &= ~0xf0; + } + register_cp_regs_for_features(cpu); arm_cpu_register_gdb_regs_for_features(cpu);