From patchwork Wed Dec 3 07:12:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chengyu Song X-Patchwork-Id: 417451 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 6EF321400A0 for ; Thu, 4 Dec 2014 01:02:32 +1100 (AEDT) Received: from localhost ([::1]:41686 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XwAVi-0003v7-LQ for incoming@patchwork.ozlabs.org; Wed, 03 Dec 2014 09:02:30 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53478) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xw4iw-0005g9-OG for qemu-devel@nongnu.org; Wed, 03 Dec 2014 02:51:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xw4iq-0003MW-5C for qemu-devel@nongnu.org; Wed, 03 Dec 2014 02:51:46 -0500 Received: from mx2.gtisc.gatech.edu ([143.215.130.82]:60172) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xw4iq-0003MN-09 for qemu-devel@nongnu.org; Wed, 03 Dec 2014 02:51:40 -0500 Received: from alternative.gtisc.gatech.edu (alternative.gtisc.gatech.edu [143.215.130.208]) by mx2.gtisc.gatech.edu (Postfix) with SMTP id 996F91BC1BB; Wed, 3 Dec 2014 07:13:16 +0000 (UTC) Received: (nullmailer pid 30389 invoked by uid 1000); Wed, 03 Dec 2014 07:13:04 -0000 From: Chengyu Song To: qemu-devel@nongnu.org Date: Wed, 3 Dec 2014 02:12:18 -0500 Message-Id: <1417590738-29072-1-git-send-email-csong84@gatech.edu> X-Mailer: git-send-email 2.1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 143.215.130.82 X-Mailman-Approved-At: Wed, 03 Dec 2014 09:01:47 -0500 Cc: Chengyu Song Subject: [Qemu-devel] [PATCH] ARM64: support access to more performance registers in AA64 mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In AA64 mode, certain system registers are access through MSR/MRS instructions instead of MCR/MRC. This patch added more such registers: /* ARMv8 manual, D8.4.10 */ PMINTENCLR_EL1 /* ARMv8 manual, D8.4.11 */ PMINTENSET_EL1 /* ARMv8 manual, D8.4.12 */ PMOVSCLR_EL0 /* ARMv8 manual, D8.4.14 */ PMSELR_EL0 /* ARMv8 manual, D8.4.15 */ PMSWINC_EL0 /* ARMv8 manual, D8.4.16 */ PMUSERENR_EL0 /* ARMv8 manual, D8.4.17 */ PMXEVCNTR_EL0 /* ARMv8 manual, D8.4.18 */ PMXEVTYPER_EL0 Signed-off-by: Chengyu Song --- target-arm/helper.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index b74d348..43b5b06 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -843,15 +843,28 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .accessfn = pmreg_access, .writefn = pmovsr_write, .raw_writefn = raw_write }, + { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .crn = 9, .crm = 12, .opc1 = 3, .opc2 = 3, + .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), + .accessfn = pmreg_access, + .writefn = pmovsr_write, + .raw_writefn = raw_write }, /* Unimplemented so WI. */ { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP }, + { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .crn = 9, .crm = 12, .opc1 = 3, .opc2 = 4, + .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP }, /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE. * We choose to RAZ/WI. */ { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, .accessfn = pmreg_access }, + { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .crn = 9, .crm = 12, .opc1 = 3, .opc2 = 5, + .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, + .accessfn = pmreg_access }, #ifndef CONFIG_USER_ONLY { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO, @@ -875,24 +888,51 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper), .accessfn = pmreg_access, .writefn = pmxevtyper_write, .raw_writefn = raw_write }, + { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .crn = 9, .crm = 13, .opc1 = 3, .opc2 = 1, + .access = PL0_RW, + .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper), + .accessfn = pmreg_access, .writefn = pmxevtyper_write, + .raw_writefn = raw_write }, /* Unimplemented, RAZ/WI. */ { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, .accessfn = pmreg_access }, + { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .crn = 9, .crm = 13, .opc1 = 3, .opc2 = 2, + .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, + .accessfn = pmreg_access }, { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, .access = PL0_R | PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), .resetvalue = 0, .writefn = pmuserenr_write, .raw_writefn = raw_write }, + { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .crn = 9, .crm = 14, .opc1 = 3, .opc2 = 0, + .access = PL0_R | PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), + .resetvalue = 0, + .writefn = pmuserenr_write, .raw_writefn = raw_write }, { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), .resetvalue = 0, .writefn = pmintenset_write, .raw_writefn = raw_write }, + { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), + .resetvalue = 0, + .writefn = pmintenset_write, .raw_writefn = raw_write }, { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), .resetvalue = 0, .writefn = pmintenclr_write, }, + { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, + .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, + .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), + .resetvalue = 0, .writefn = pmintenclr_write, }, { .name = "VBAR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .writefn = vbar_write,