From patchwork Mon Nov 17 16:47:55 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 411745 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id A111E14012B for ; Tue, 18 Nov 2014 04:09:10 +1100 (AEDT) Received: from localhost ([::1]:49103 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XqPnY-0004N1-Nt for incoming@patchwork.ozlabs.org; Mon, 17 Nov 2014 12:09:08 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60140) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XqPU6-0002Tn-B6 for qemu-devel@nongnu.org; Mon, 17 Nov 2014 11:49:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XqPTv-0007Hv-EZ for qemu-devel@nongnu.org; Mon, 17 Nov 2014 11:49:02 -0500 Received: from mail-pa0-f49.google.com ([209.85.220.49]:42076) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XqPTo-0007GZ-Uf for qemu-devel@nongnu.org; Mon, 17 Nov 2014 11:48:51 -0500 Received: by mail-pa0-f49.google.com with SMTP id eu11so813375pac.22 for ; Mon, 17 Nov 2014 08:48:44 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tnDUaUT6ZZhTahuIO5B2YG6WKTqTU/StBdzikDMX7C0=; b=He5OY5LC95XAMcoqqvlos7wVYWrxKMnlfYno/fyfV0i1awfrA3LpGN2QVCuzBjMzDY dkIBlSRnC30Ea1SX7qKJOA/jaKeqk0ZuFoqvSCAepeVM5XrnVOaj/ZH+5pfSxHYVGL8U kyInmVHb8pTUjqRfE+RRKD8zyHv3/UCV89NV9fSOH4rSSZFR7FiG/7q+x9ojhHEcFABK pAp0RhCzFRm6JhYXSSC98/SGw5GYKLPCo1beU1eTFRwXaAohOyOucbJdIGLJ7ESB2Sdg 17q3sA7ydR91eO5rInvjx0VCGgaO3HHtQbLEgQkpWOySzOPaqZZq5ev8zj9SyHpdGKih dWMg== X-Gm-Message-State: ALoCoQlDrlZd+pzWrF3bH4yDM8/9mIjxtbp8oy2cUVn7X86KebnR8i+7s3ti9SJ4UHwPwTxKsLT5 X-Received: by 10.70.87.227 with SMTP id bb3mr30983721pdb.71.1416242924489; Mon, 17 Nov 2014 08:48:44 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id r2sm18499056pdi.60.2014.11.17.08.48.43 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 17 Nov 2014 08:48:43 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Mon, 17 Nov 2014 10:47:55 -0600 Message-Id: <1416242878-876-24-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1416242878-876-1-git-send-email-greg.bellows@linaro.org> References: <1416242878-876-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.49 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v11 23/26] target-arm: make VBAR banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org When EL3 is running in Aarch32 (or ARMv7 with Security Extensions) VBAR has a secure and a non-secure instance, which are mapped to VBAR_EL1 and VBAR_EL3. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v8 -> v9 - Revert unnecessary CPreg definition changes v5 -> v6 - Changed _el field variants to be array based - Merged VBAR and VBAR_EL1 reginfo entries v3 -> v4 - Fix vbar union/structure definition - Revert back to array-based vbar definition combined with v7 naming --- target-arm/cpu.h | 10 +++++++++- target-arm/helper.c | 5 +++-- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 2f8d607..fc64497 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -297,7 +297,15 @@ typedef struct CPUARMState { uint32_t c9_pmuserenr; /* perf monitor user enable */ uint32_t c9_pminten; /* perf monitor interrupt enables */ uint64_t mair_el1; - uint64_t vbar_el[4]; /* vector base address register */ + union { /* vector base address register */ + struct { + uint64_t _unused_vbar; + uint64_t vbar_ns; + uint64_t hvbar; + uint64_t vbar_s; + }; + uint64_t vbar_el[4]; + }; uint32_t mvbar; /* (monitor) vector base address register */ uint32_t c13_fcse; /* FCSE PID. */ uint64_t contextidr_el1; /* Context ID. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 081c00e..69f2e68 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -911,7 +911,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { { .name = "VBAR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .writefn = vbar_write, - .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]), + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), + offsetof(CPUARMState, cp15.vbar_ns) }, .resetvalue = 0 }, { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, @@ -4401,7 +4402,7 @@ void arm_cpu_do_interrupt(CPUState *cs) * This register is only followed in non-monitor mode, and is banked. * Note: only bits 31:5 are valid. */ - addr += env->cp15.vbar_el[1]; + addr += A32_BANKED_CURRENT_REG_GET(env, vbar); } if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {