diff mbox

target-mips: fix multiple TCG registers covering same data

Message ID 1415357001-52690-1-git-send-email-yongbok.kim@imgtec.com
State New
Headers show

Commit Message

Yongbok Kim Nov. 7, 2014, 10:43 a.m. UTC 
Avoid to allocate different TCG registers for the FPU registers
that are mapped on the MSA vectore registers.

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
---
 target-mips/translate.c |    8 +++-----
 1 files changed, 3 insertions(+), 5 deletions(-)

Comments

Richard Henderson Nov. 7, 2014, 10:57 a.m. UTC | #1 
On 11/07/2014 11:43 AM, Yongbok Kim wrote:
> Avoid to allocate different TCG registers for the FPU registers
> that are mapped on the MSA vectore registers.
> 
> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
> ---
>  target-mips/translate.c |    8 +++-----
>  1 files changed, 3 insertions(+), 5 deletions(-)

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~
diff mbox

Patch

diff --git a/target-mips/translate.c b/target-mips/translate.c
index b43b286..95d8071 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -20200,14 +20200,12 @@  void mips_tcg_init(void)
                                         regnames[i]);
 
     for (i = 0; i < 32; i++) {
-        int off = offsetof(CPUMIPSState, active_fpu.fpr[i]);
-        fpu_f64[i] = tcg_global_mem_new_i64(TCG_AREG0, off, fregnames[i]);
-    }
-
-    for (i = 0; i < 32; i++) {
         int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
         msa_wr_d[i * 2] =
                 tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2]);
+        /* The scalar floating-point unit (FPU) registers are mapped on
+         * the MSA vector registers. */
+        fpu_f64[i] = msa_wr_d[i * 2];
         off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
         msa_wr_d[i * 2 + 1] =
                 tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2 + 1]);