From patchwork Thu Oct 30 21:28:48 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 405367 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 9162214007D for ; Sat, 1 Nov 2014 03:09:02 +1100 (AEDT) Received: from localhost ([::1]:38684 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkEl1-0007Fh-WD for incoming@patchwork.ozlabs.org; Fri, 31 Oct 2014 12:09:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48735) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkE64-0003ca-N5 for qemu-devel@nongnu.org; Fri, 31 Oct 2014 11:27:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XjxHi-00054X-GL for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:40 -0400 Received: from mail-pd0-f173.google.com ([209.85.192.173]:33247) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjxHi-00053r-7T for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:34 -0400 Received: by mail-pd0-f173.google.com with SMTP id v10so5940688pde.32 for ; Thu, 30 Oct 2014 14:29:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oPv5LvhB4EduQAZ/ulB1f1iiK3n9F7s1dgZy0o33u6w=; b=a+etqM27g+BzDDIGTDcXDDpO9PsSULDocLbi0bMCnj8ZqgUGRQvrdVK0yHH5MATYFR ErfXMtwR+YLCH20oDoz5+029VKTRvMGiKOAsUwaWnDcVyMEEvzBmG3xDXr6rGsgeg/4c WX+NgBdXj/b4Tc4/Ouko7ZibkAglcx2zmk6BuJaEIHJ/0s3CmrlUZqLznbA7Iu0ucppW g7y/ZInsxMu2DqJnRRI2ZknHYz8jS+tkZQFdFeOww6su+D2FrIOSyiWJzgsnmjdAnAhC KWAkLC0c+pBDbzdzeAuD6qb6UXJVzpXAR6aY/Ae/3Mp5488uVC2eVYvyEF4NySh0tOSA BR1g== X-Gm-Message-State: ALoCoQlCo7lBzsrguTq6WrBOIM+2Dx4nstl0Jy45ZzZLy+Ekg05Pze7MpfeK2Vmke2Hvj9UTjZaA X-Received: by 10.68.213.138 with SMTP id ns10mr17275697pbc.50.1414704573581; Thu, 30 Oct 2014 14:29:33 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id o5sm8017713pdr.50.2014.10.30.14.29.32 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 30 Oct 2014 14:29:33 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Thu, 30 Oct 2014 16:28:48 -0500 Message-Id: <1414704538-17103-18-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> References: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.173 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v8 17/27] target-arm: add TCR_EL3 and make TTBCR banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Adds TCR_EL3 system register and makes existing TTBCR banked. Adjust translation functions to use TCR/TTBCR instance depending on CPU state. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- v5 -> v6 - Changed _el field variants to be array based v4 -> v5 - Changed c2_mask updates to use the TTBCR cpreg bank flag for selcting the secure bank instead of the A32_BANKED_CURRENT macro. This more accurately chooses the correct bank matching that of the TTBCR being accessed. --- target-arm/cpu.h | 10 +++++++++- target-arm/helper.c | 48 +++++++++++++++++++++++++++++++++++------------- target-arm/internals.h | 2 +- 3 files changed, 45 insertions(+), 15 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index fe96869..f125bdd 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -217,7 +217,15 @@ typedef struct CPUARMState { }; uint64_t ttbr1_el[4]; }; - uint64_t c2_control; /* MMU translation table base control. */ + union { /* MMU translation table base control. */ + struct { + uint64_t _unused_ttbcr_0; + uint64_t ttbcr_ns; + uint64_t _unused_ttbcr_1; + uint64_t ttbcr_s; + }; + uint64_t tcr_el[4]; + }; uint32_t c2_mask; /* MMU translation table base selection mask. */ uint32_t c2_base_mask; /* MMU translation table base 0 mask. */ uint32_t c2_data; /* MPU data cachable bits. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 598f0d1..896b40d 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1659,11 +1659,12 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, .access = PL1_RW, .writefn = vmsa_tcr_el1_write, .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, - .fieldoffset = offsetof(CPUARMState, cp15.c2_control) }, + .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write, .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write, - .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) }, + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ttbcr_s), + offsetoflow32(CPUARMState, cp15.ttbcr_ns) } }, /* 64-bit FAR; this entry also gives us the AArch32 DFAR */ { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, @@ -2349,6 +2350,11 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 6, .opc2 = 0, .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) }, + { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 6, .opc2 = 2, + .access = PL3_RW, .writefn = vmsa_tcr_el1_write, + .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, + .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, @@ -4435,13 +4441,13 @@ static bool get_level1_table_address(CPUARMState *env, uint32_t *table, * table registers. */ if (address & env->cp15.c2_mask) { - if ((env->cp15.c2_control & TTBCR_PD1)) { + if (A32_BANKED_CURRENT_REG_GET(env, ttbcr) & TTBCR_PD1) { /* Translation table walk disabled for TTBR1 */ return false; } *table = A32_BANKED_CURRENT_REG_GET(env, ttbr1) & 0xffffc000; } else { - if ((env->cp15.c2_control & TTBCR_PD0)) { + if (A32_BANKED_CURRENT_REG_GET(env, ttbcr) & TTBCR_PD0) { /* Translation table walk disabled for TTBR0 */ return false; } @@ -4701,13 +4707,29 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address, int32_t va_size = 32; int32_t tbi = 0; uint32_t cur_el = arm_current_el(env); + uint64_t tcr; - if (arm_el_is_aa64(env, 1)) { + if (arm_el_is_aa64(env, 3)) { + switch (cur_el) { + case 3: + tcr = env->cp15.tcr_el[3]; + break; + case 1: + case 0: + default: + tcr = env->cp15.tcr_el[1]; + } + + } else { + tcr = A32_BANKED_CURRENT_REG_GET(env, ttbcr); + } + + if (arm_el_is_aa64(env, 1) && (cur_el == 0 || cur_el == 1)) { va_size = 64; if (extract64(address, 55, 1)) - tbi = extract64(env->cp15.c2_control, 38, 1); + tbi = extract64(tcr, 38, 1); else - tbi = extract64(env->cp15.c2_control, 37, 1); + tbi = extract64(tcr, 37, 1); tbi *= 8; } @@ -4716,12 +4738,12 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address, * This is a Non-secure PL0/1 stage 1 translation, so controlled by * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: */ - uint32_t t0sz = extract32(env->cp15.c2_control, 0, 6); + uint32_t t0sz = extract32(tcr, 0, 6); if (arm_el_is_aa64(env, 1)) { t0sz = MIN(t0sz, 39); t0sz = MAX(t0sz, 16); } - uint32_t t1sz = extract32(env->cp15.c2_control, 16, 6); + uint32_t t1sz = extract32(tcr, 16, 6); if (arm_el_is_aa64(env, 1)) { t1sz = MIN(t1sz, 39); t1sz = MAX(t1sz, 16); @@ -4765,10 +4787,10 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address, } else { ttbr = A32_BANKED_CURRENT_REG_GET(env, ttbr0); } - epd = extract32(env->cp15.c2_control, 7, 1); + epd = extract32(tcr, 7, 1); tsz = t0sz; - tg = extract32(env->cp15.c2_control, 14, 2); + tg = extract32(tcr, 14, 2); if (tg == 1) { /* 64KB pages */ granule_sz = 13; } @@ -4777,10 +4799,10 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address, } } else { ttbr = A32_BANKED_CURRENT_REG_GET(env, ttbr1); - epd = extract32(env->cp15.c2_control, 23, 1); + epd = extract32(tcr, 23, 1); tsz = t1sz; - tg = extract32(env->cp15.c2_control, 30, 2); + tg = extract32(tcr, 30, 2); if (tg == 3) { /* 64KB pages */ granule_sz = 13; } diff --git a/target-arm/internals.h b/target-arm/internals.h index 2dff4ff..8c451c6 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -155,7 +155,7 @@ static inline bool extended_addresses_enabled(CPUARMState *env) { return arm_el_is_aa64(env, 1) || ((arm_feature(env, ARM_FEATURE_LPAE) - && (env->cp15.c2_control & TTBCR_EAE))); + && (A32_BANKED_CURRENT_REG_GET(env, ttbcr) & TTBCR_EAE))); } /* Valid Syndrome Register EC field values */