From patchwork Tue Oct 21 16:55:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 401635 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 0067C14001A for ; Wed, 22 Oct 2014 04:17:14 +1100 (AEDT) Received: from localhost ([::1]:52597 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgd3Z-0007Le-37 for incoming@patchwork.ozlabs.org; Tue, 21 Oct 2014 13:17:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42256) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjO-00076f-MX for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XgcjJ-0006zW-BW for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:22 -0400 Received: from mail-qg0-f46.google.com ([209.85.192.46]:45651) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjJ-0006zD-33 for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:17 -0400 Received: by mail-qg0-f46.google.com with SMTP id z60so1184236qgd.33 for ; Tue, 21 Oct 2014 09:56:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=52jFFIgfxx6GODDZhDopyHmGKTvzX25tt8ukeIC/VK0=; b=KbL/iIwFdSG1ZrbScaIW4Tz5L3xGt6jJeE1BYpo5IMQUHlIMryStQVYAM68DjRQxIc 6KzX5dS041yvus3UmG6E/QzdkGCo1MCbNq827x8FZ5s+2HzRUBg9sInmBqLZ34nvN25/ m9/yFv3/1B/qZxavTWeuN1srIcr5dSkFAwi7dDHql9LgHuS4nqbKQex8U6D+wvDE8f3z nAot59RSy05V5vDo+T2COuU4U6cWowVHU5iqo0kkgEaoCoTdfRIPh48SROEKw6ugfaOr 9i2aE9OpQh9myMLyeEQvcWgXGpH/XDph1O9Q1dPyNVYiKmJVMHRHiKb2+RspeJS16w2i jRzg== X-Gm-Message-State: ALoCoQmMP/BfbDr/0Y0gAY6bxFgcdRROuobWKl4f+ZXVxiUDYvsuBxLcHFyuKt9RqDCy2bySNrqW X-Received: by 10.140.29.134 with SMTP id b6mr44645207qgb.23.1413910576637; Tue, 21 Oct 2014 09:56:16 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com ([67.52.129.61]) by mx.google.com with ESMTPSA id a3sm11122116qaa.49.2014.10.21.09.56.15 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 21 Oct 2014 09:56:16 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 21 Oct 2014 11:55:40 -0500 Message-Id: <1413910544-20150-29-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> References: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.46 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v7 28/32] target-arm: make IFAR/DFAR banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler When EL3 is running in AArch32 (or ARMv7 with Security Extensions) IFAR and DFAR have a secure and a non-secure instance. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows ----------------- v3 -> v4 - Revert to array-based notation of far_el in combination with v7 naming Signed-off-by: Greg Bellows --- target-arm/cpu.c | 2 +- target-arm/cpu.h | 19 ++++++++++++++++++- target-arm/helper.c | 20 +++++++++++--------- 3 files changed, 30 insertions(+), 11 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index fdb6de4..63573c6 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -522,7 +522,7 @@ static void arm1026_initfn(Object *obj) ARMCPRegInfo ifar = { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, - .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]), + .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), .resetvalue = 0 }; define_one_arm_cp_reg(cpu, &ifar); diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 1f12a2c..600528e 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -270,7 +270,24 @@ typedef struct CPUARMState { uint64_t esr_el[4]; }; uint32_t c6_region[8]; /* MPU base/size registers. */ - uint64_t far_el[4]; /* Fault address registers. */ + union { /* Fault address registers. */ + struct { + uint64_t _unused_far0; +#ifdef HOST_WORDS_BIGENDIAN + uint32_t ifar_ns; + uint32_t dfar_ns; + uint32_t ifar_s; + uint32_t dfar_s; +#else + uint32_t dfar_ns; + uint32_t ifar_ns; + uint32_t dfar_s; + uint32_t ifar_s; +#endif + uint64_t _unused_far3;; + }; + uint64_t far_el[4]; + }; uint64_t par_el1; /* Translation result. */ uint32_t c9_insn; /* Cache lockdown registers. */ uint32_t c9_data; diff --git a/target-arm/helper.c b/target-arm/helper.c index 01f4ce7..f46bc2a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -567,7 +567,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] = { .access = PL0_W, .type = ARM_CP_NOP }, { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, .access = PL1_RW, - .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]), + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s), + offsetof(CPUARMState, cp15.ifar_ns) }, .resetvalue = 0, }, /* Watchpoint Fault Address Register : should actually only be present * for 1136, 1176, 11MPCore. @@ -1694,11 +1695,14 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write, .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ttbcr_s), offsetoflow32(CPUARMState, cp15.ttbcr_ns) } }, - /* 64-bit FAR; this entry also gives us the AArch32 DFAR */ - { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH, + { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, + .access = PL1_RW, .resetvalue = 0, + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), + offsetof(CPUARMState, cp15.dfar_ns) } }, + { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), - .resetvalue = 0, }, + .access = PL1_RW, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]) }, REGINFO_SENTINEL }; @@ -4358,8 +4362,7 @@ void arm_cpu_do_interrupt(CPUState *cs) /* Fall through to prefetch abort. */ case EXCP_PREFETCH_ABORT: A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); - env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 32, 32, - env->exception.vaddress); + A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", env->exception.fsr, (uint32_t)env->exception.vaddress); new_mode = ARM_CPU_MODE_ABT; @@ -4369,8 +4372,7 @@ void arm_cpu_do_interrupt(CPUState *cs) break; case EXCP_DATA_ABORT: A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); - env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 0, 32, - env->exception.vaddress); + A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", env->exception.fsr, (uint32_t)env->exception.vaddress);