From patchwork Tue Oct 21 16:55:39 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 401631 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id DB4FD14001A for ; Wed, 22 Oct 2014 04:13:33 +1100 (AEDT) Received: from localhost ([::1]:52569 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgczz-0001VE-RH for incoming@patchwork.ozlabs.org; Tue, 21 Oct 2014 13:13:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42254) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjO-00076b-LR for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XgcjJ-0006zM-5s for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:22 -0400 Received: from mail-qg0-f51.google.com ([209.85.192.51]:32993) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjI-0006z4-MZ for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:16 -0400 Received: by mail-qg0-f51.google.com with SMTP id z107so1200700qgd.10 for ; Tue, 21 Oct 2014 09:56:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mKXeZ0uZ87eEvppG83XLz7Mf5Cw3kTZurAZq3MQaPUw=; b=FdC2OlPjDi7g1L+Kh6LC0zFGqgKaphbWdbD6yXMZK17Z355rr5rk3p25jDCBcNNgdb hNdsJezz2G1yegojasoHPR7cyX0bF6yOSli92f77mva3Lfi9mL37psJOPX7HOPfLtIYu xozmS4hOGawS3Mgyz/30R7pEoLPdRjUSsi43u4cfA0IDtOQALX63O0CNqQMWeFBpmrdk B+QGXSsTtwdROwdDbf8VabG0nHX8oozMz3DdT5uHoL3N8oLvzMTzkkTbtzpJxRomsxA+ mypkawbsjQ4/6i5GXWPOFBOE7oNWD9vFLZXH9ThuC3LOHNtZM/P2lKkSdPHBlD6abdvn MXWg== X-Gm-Message-State: ALoCoQnVUBLNA7sjW5xULg+TBzYDbUShuFBL+t8SDSRpP+hzN6QY9e5jLv3od2v1LbzYDtjiYy84 X-Received: by 10.229.213.5 with SMTP id gu5mr47674954qcb.13.1413910575809; Tue, 21 Oct 2014 09:56:15 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com ([67.52.129.61]) by mx.google.com with ESMTPSA id a3sm11122116qaa.49.2014.10.21.09.56.15 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 21 Oct 2014 09:56:15 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 21 Oct 2014 11:55:39 -0500 Message-Id: <1413910544-20150-28-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> References: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.51 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v7 27/32] target-arm: make DFSR banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler When EL3 is running in AArch32 (or ARMv7 with Security Extensions) DFSR has a secure and a non-secure instance. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --------------- v3 -> v4 - Reverted esr/dfsr back to array-based notation as a union with v7 naming. Signed-off-by: Greg Bellows --- target-arm/cpu.h | 10 +++++++++- target-arm/helper.c | 7 ++++--- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 261b881..1f12a2c 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -260,7 +260,15 @@ typedef struct CPUARMState { uint32_t ifsr32_el2; }; }; - uint64_t esr_el[4]; + union { + struct { + uint64_t _unused_dfsr; + uint64_t dfsr_ns; + uint64_t hsr; + uint64_t dfsr_s; + }; + uint64_t esr_el[4]; + }; uint32_t c6_region[8]; /* MPU base/size registers. */ uint64_t far_el[4]; /* Fault address registers. */ uint64_t par_el1; /* Translation result. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 7498f71..01f4ce7 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1663,7 +1663,8 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, static const ARMCPRegInfo vmsa_cp_reginfo[] = { { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, - .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), + offsetoflow32(CPUARMState, cp15.dfsr_ns) }, .resetfn = arm_cp_reset_ignore, }, { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, .resetvalue = 0, @@ -4367,11 +4368,11 @@ void arm_cpu_do_interrupt(CPUState *cs) offset = 4; break; case EXCP_DATA_ABORT: - env->cp15.esr_el[1] = env->exception.fsr; + A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 0, 32, env->exception.vaddress); qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", - (uint32_t)env->cp15.esr_el[1], + env->exception.fsr, (uint32_t)env->exception.vaddress); new_mode = ARM_CPU_MODE_ABT; addr = 0x10;