From patchwork Fri Oct 10 16:03:41 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 398726 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 0F83E140076 for ; Sat, 11 Oct 2014 03:26:13 +1100 (EST) Received: from localhost ([::1]:49646 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xcd19-0001rW-3d for incoming@patchwork.ozlabs.org; Fri, 10 Oct 2014 12:26:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35309) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XccgA-0007Uq-6U for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xccg4-0008A0-QT for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:30 -0400 Received: from mail-oi0-f50.google.com ([209.85.218.50]:33384) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xccg4-00089i-L9 for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:24 -0400 Received: by mail-oi0-f50.google.com with SMTP id i138so7201601oig.9 for ; Fri, 10 Oct 2014 09:04:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=DhQheDzjaThnxoRYvYdnhSaerz01oGPfmnKujti9s3g=; b=SW51qjCaEJ3kR6B1jg/wXa0orDdlA+nFzVeiaqx2Js3s5tFovy7j+cqyQtLGtpw3Mi U9qcFJHQIrCEa3uaMorq6nSp4Vk11DB5E0kwH+xuhYi1Z0jFHOJU0n4z7I+gB/6AT99S C7nmVU7w3a4LO61BGC3ul3w9Hsf8BiRdj16+4CR4v9zQcp7mgoD1J1mkzpizO5fk2J0z MpciOGPRzFxANEgsz+oQ/hxdXPxNALPyFMfZ2meMfShxjM4w7mBpK/Q8ZqHa0EUEDWFa Ch8TLEEtyEbQt4Q37eALQuokbASo7prQiM4g/lzICxYd9rKeMtJpL2DYU/MHZmLQLYUB S3Jw== X-Gm-Message-State: ALoCoQkFGP6U+590EzmgXR3Ink7/ZBu6WvbSwP0yW46FxcgzRBleNKrYb3BD7gsMHXCOjwoEqMfr X-Received: by 10.202.2.73 with SMTP id 70mr772436oic.133.1412957064319; Fri, 10 Oct 2014 09:04:24 -0700 (PDT) Received: from gbellows-linaro.bellowshome.net (99-179-1-128.lightspeed.austtx.sbcglobal.net. [99.179.1.128]) by mx.google.com with ESMTPSA id d6sm5382455obt.12.2014.10.10.09.04.23 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 10 Oct 2014 09:04:23 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Fri, 10 Oct 2014 11:03:41 -0500 Message-Id: <1412957023-11105-31-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1412957023-11105-1-git-send-email-greg.bellows@linaro.org> References: <1412957023-11105-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.218.50 Subject: [Qemu-devel] [PATCH v6 30/32] target-arm: make c13 cp regs banked (FCSEIDR, ...) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler When EL3 is running in AArch32 (or ARMv7 with Security Extensions) FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure and a non-secure instance. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows ========== v5 -> v6 - Changed _el field variants to be array based - Rework data layout for correct aliasing - Merged CONTEXTIDR and CONTEXTIDR_EL1 reginfo entries v3 -> v4 - Fix tpidrprw mapping --- target-arm/cpu.h | 35 ++++++++++++++++++++++++++++++----- target-arm/helper.c | 37 ++++++++++++++++++++++--------------- target-arm/op_helper.c | 2 +- 3 files changed, 53 insertions(+), 21 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 4804ff1..e8ede63 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -316,11 +316,36 @@ typedef struct CPUARMState { uint64_t vbar_el[4]; }; uint64_t mvbar; /* (monitor) vector base address register */ - uint32_t c13_fcse; /* FCSE PID. */ - uint64_t contextidr_el1; /* Context ID. */ - uint64_t tpidr_el0; /* User RW Thread register. */ - uint64_t tpidrro_el0; /* User RO Thread register. */ - uint64_t tpidr_el1; /* Privileged Thread register. */ + struct { /* FCSE PID. */ + uint32_t fcseidr_ns; + uint32_t fcseidr_s; + }; + union { /* Context ID. */ + struct { + uint64_t _unused_contextidr; + uint64_t contextidr_ns; + uint64_t contextidr_s; + }; + uint64_t contextidr_el[2]; + }; + union { /* User RW Thread register. */ + struct { + uint64_t tpidrurw_ns; + uint64_t tpidrprw_ns; + uint64_t htpidr; + uint64_t _tpidr_el3; + }; + uint64_t tpidr_el[4]; + }; + /* The secure banks of these registers don't map anywhere */ + uint64_t tpidrurw_s; + uint64_t tpidrprw_s; + uint64_t tpidruro_s; + + union { /* User RO Thread register. */ + uint64_t tpidruro_ns; + uint64_t tpidrro_el[1]; + }; uint64_t c14_cntfrq; /* Counter Frequency register */ uint64_t c14_cntkctl; /* Timer Control register */ ARMGenericTimer c14_timer[NUM_GTIMERS]; diff --git a/target-arm/helper.c b/target-arm/helper.c index 1e211c4..d05eb4d 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -420,12 +420,15 @@ static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, static const ARMCPRegInfo cp_reginfo[] = { { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse), + .access = PL1_RW, + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.fcseidr_s), + offsetof(CPUARMState, cp15.fcseidr_ns) }, .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, { .name = "CONTEXTIDR", .state = ARM_CP_STATE_BOTH, - .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, + .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, .access = PL1_RW, - .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el1), + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.contextidr_s), + offsetof(CPUARMState, cp15.contextidr_ns) }, .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, REGINFO_SENTINEL }; @@ -1038,23 +1041,27 @@ static const ARMCPRegInfo v6k_cp_reginfo[] = { { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, .access = PL0_RW, - .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 }, + .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 }, { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, - .access = PL0_RW, - .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0), - .resetfn = arm_cp_reset_ignore }, + .access = PL0_RW, .resetvalue = 0, + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), + offsetoflow32(CPUARMState, cp15.tpidrurw_ns) } }, { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, - .access = PL0_R|PL1_W, - .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 }, + .access = PL0_R|PL1_W, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]) }, { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, - .access = PL0_R|PL1_W, - .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0), - .resetfn = arm_cp_reset_ignore }, - { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH, + .access = PL0_R|PL1_W, .resetvalue = 0, + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), + offsetoflow32(CPUARMState, cp15.tpidruro_ns) } }, + { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, .access = PL1_RW, - .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 }, + .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 }, + { .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4, + .access = PL1_RW, .resetvalue = 0, + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), + offsetoflow32(CPUARMState, cp15.tpidrprw_ns) } }, REGINFO_SENTINEL }; @@ -5102,7 +5109,7 @@ static inline int get_phys_addr(CPUARMState *env, target_ulong address, /* Fast Context Switch Extension. */ if (address < 0x02000000) - address += env->cp15.c13_fcse; + address += A32_BANKED_CURRENT_REG_GET(env, fcseidr); if ((sctlr & SCTLR_M) == 0) { /* MMU/MPU disabled. */ diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 6a093d6..7383d79 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -556,7 +556,7 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn) * short descriptor format (in which case it holds both PROCID and ASID), * since we don't implement the optional v7 context ID masking. */ - contextidr = extract64(env->cp15.contextidr_el1, 0, 32); + contextidr = extract64(env->cp15.contextidr_el[1], 0, 32); switch (bt) { case 3: /* linked context ID match */