From patchwork Fri Oct 10 16:03:13 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 398696 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 232A81400AB for ; Sat, 11 Oct 2014 03:04:52 +1100 (EST) Received: from localhost ([::1]:49376 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XccgT-0007zU-3s for incoming@patchwork.ozlabs.org; Fri, 10 Oct 2014 12:04:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34843) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xccfi-0006lb-EP for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xccfd-0007wa-Hl for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:02 -0400 Received: from mail-oi0-f48.google.com ([209.85.218.48]:32963) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xccfd-0007wV-Dk for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:03:57 -0400 Received: by mail-oi0-f48.google.com with SMTP id g201so7088675oib.7 for ; Fri, 10 Oct 2014 09:03:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=vhMnR3W1+2qjGSjizTksfCN2HAnhnqpA7mhoLn60koU=; b=YFqk9Z2LcXKZmfSeOcyQ0f+WmmubdaP/bx25tIS+N3AIAM085QmidzaR1YFWbkqwpw VUWz+xCUBQ9tkgAKPMAYKE6g80lkRPD+VbHjcf64oA0yPmDg3NnTGkhZHq3gjqpxlRgK YqpbFBc76rWCV5o1VWWKkWRc5EYLz6I7Tn1ZSKNVld+F0ZD5vonSHIWT2Gl3EveTQZfj i37sJaPv8bzESBcR9XjYBY4nT//9095s4IrGeNR0/2IYp72v3zwD2fsYTigeVSsLokP6 zImSa3TdeFmWa9OHmXpWGlKiOvhtWc8ZlzGVgdRkbjW+IrsAQ2IPrDiXD4pd2dyul1Xd iPag== X-Gm-Message-State: ALoCoQnJJubaupVQe6Sxx6wjlWMtokQNVjsI1LUzgi4USWMwIN0/GklBbf0K4SjGe6d7/VK/WKSK X-Received: by 10.202.11.72 with SMTP id 69mr5288546oil.40.1412957036908; Fri, 10 Oct 2014 09:03:56 -0700 (PDT) Received: from gbellows-linaro.bellowshome.net (99-179-1-128.lightspeed.austtx.sbcglobal.net. [99.179.1.128]) by mx.google.com with ESMTPSA id d6sm5382455obt.12.2014.10.10.09.03.55 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 10 Oct 2014 09:03:56 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Fri, 10 Oct 2014 11:03:13 -0500 Message-Id: <1412957023-11105-3-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1412957023-11105-1-git-send-email-greg.bellows@linaro.org> References: <1412957023-11105-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.218.48 Subject: [Qemu-devel] [PATCH v6 02/32] target-arm: add arm_is_secure() function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler arm_is_secure() function allows to determine CPU security state if the CPU implements Security Extensions/EL3. arm_is_secure_below_el3() returns true if CPU is in secure state below EL3. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows ========== v5 -> v6 - Broaden CONFIG_USER conditional - Merge resulting false returns with common comment - Globally change Aarch# to AArch# - Replace direct access of env->aarch64 with is_a64() --- target-arm/cpu.h | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 81fffd2..4f6db0f 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -753,6 +753,48 @@ static inline int arm_feature(CPUARMState *env, int feature) return (env->features & (1ULL << feature)) != 0; } +#if !defined(CONFIG_USER_ONLY) +/* Return true if exception level below EL3 is in secure state */ +static inline bool arm_is_secure_below_el3(CPUARMState *env) +{ + if (arm_feature(env, ARM_FEATURE_EL3)) { + return !(env->cp15.scr_el3 & SCR_NS); + } else { + /* If EL2 is not supported then the secure state is implementation + * defined, in which case QEMU defaults to non-secure. + */ + return false; + } +} + +/* Return true if the processor is in secure state */ +static inline bool arm_is_secure(CPUARMState *env) +{ + if (arm_feature(env, ARM_FEATURE_EL3)) { + if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { + /* CPU currently in AArch64 state and EL3 */ + return true; + } else if (!is_a64(env) && + (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { + /* CPU currently in AArch32 state and monitor mode */ + return true; + } + } + return arm_is_secure_below_el3(env); +} + +#else +static inline bool arm_is_secure_below_el3(CPUARMState *env) +{ + return false; +} + +static inline bool arm_is_secure(CPUARMState *env) +{ + return false; +} +#endif + /* Return true if the specified exception level is running in AArch64 state. */ static inline bool arm_el_is_aa64(CPUARMState *env, int el) {