From patchwork Fri Oct 10 16:03:12 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 398700 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8F21814009B for ; Sat, 11 Oct 2014 03:07:10 +1100 (EST) Received: from localhost ([::1]:49399 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xccii-0003Ay-Kb for incoming@patchwork.ozlabs.org; Fri, 10 Oct 2014 12:07:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34886) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xccfk-0006mX-89 for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xccfc-0007w1-Ez for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:04 -0400 Received: from mail-oi0-f46.google.com ([209.85.218.46]:48333) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xccfc-0007vo-Aw for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:03:56 -0400 Received: by mail-oi0-f46.google.com with SMTP id h136so7119273oig.5 for ; Fri, 10 Oct 2014 09:03:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=4qitSF2WF+6F4ku1qneT8pFaglPDIIChbkSP6Y63MrY=; b=XhbOlR7bSlxbMqOt41qVSPIkekTrE/W9iJWFrNFMOz9qr69obkpyhkwU9CBG4qr73/ YLWua8EZeR8jDuPQF/BNXCwHldBbzzrnx0xaf0Oo9i59WTRJtfpvJu31IT+w0X+gwe4P SHiret/rnUd7mXGOZSVeqOoLN2RKWtYsJ1gMm1vLWxXvhgtg3mGTIZohKoy+wtyLMaj+ RA4w8M2RTEYiRgrUpfXUQhMBIJW8VmGkeusPmE1EmDQE7AiBqAaLsXk2QnmB4U2fWMZG TjBQRGMQDTdeFAvxfAu9TCDHLL6kzbMgfv4mKjaCF/KXIgRb04xVAXtLV/htZuSUnnGg B34g== X-Gm-Message-State: ALoCoQmOmjU0DpZPHjdSj6GfbhgjVF+dqJC5CBYpVWkbAWUxwCrKJPMlzSgEqxlV+W5u4yibrWGR X-Received: by 10.60.97.137 with SMTP id ea9mr5614212oeb.12.1412957035710; Fri, 10 Oct 2014 09:03:55 -0700 (PDT) Received: from gbellows-linaro.bellowshome.net (99-179-1-128.lightspeed.austtx.sbcglobal.net. [99.179.1.128]) by mx.google.com with ESMTPSA id d6sm5382455obt.12.2014.10.10.09.03.54 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 10 Oct 2014 09:03:55 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Fri, 10 Oct 2014 11:03:12 -0500 Message-Id: <1412957023-11105-2-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1412957023-11105-1-git-send-email-greg.bellows@linaro.org> References: <1412957023-11105-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.218.46 Subject: [Qemu-devel] [PATCH v6 01/32] target-arm: increase arrays of registers R13 & R14 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Increasing banked_r13 and banked_r14 to store LR_mon and SP_mon (bank index 7). Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell ========== v5 -> v6 - Updated vmstate_arm_cpu versioning from 20 to 21 --- target-arm/cpu.h | 4 ++-- target-arm/machine.c | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 65a3417..81fffd2 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -153,8 +153,8 @@ typedef struct CPUARMState { /* Banked registers. */ uint64_t banked_spsr[8]; - uint32_t banked_r13[6]; - uint32_t banked_r14[6]; + uint32_t banked_r13[8]; + uint32_t banked_r14[8]; /* These hold r8-r12. */ uint32_t usr_regs[5]; diff --git a/target-arm/machine.c b/target-arm/machine.c index ddb7d05..f1c903d 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -222,8 +222,8 @@ static int cpu_post_load(void *opaque, int version_id) const VMStateDescription vmstate_arm_cpu = { .name = "cpu", - .version_id = 20, - .minimum_version_id = 20, + .version_id = 21, + .minimum_version_id = 21, .pre_save = cpu_pre_save, .post_load = cpu_post_load, .fields = (VMStateField[]) { @@ -238,8 +238,8 @@ const VMStateDescription vmstate_arm_cpu = { }, VMSTATE_UINT32(env.spsr, ARMCPU), VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8), - VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6), - VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6), + VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8), + VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8), VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5), VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4),