From patchwork Tue Sep 30 21:49:17 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 395326 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 0D785140218 for ; Wed, 1 Oct 2014 07:51:23 +1000 (EST) Received: from localhost ([::1]:46541 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5KI-0001iq-7l for incoming@patchwork.ozlabs.org; Tue, 30 Sep 2014 17:51:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42887) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5JA-0000IP-MI for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XZ5J5-0003OO-8w for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:08 -0400 Received: from mail-pd0-f179.google.com ([209.85.192.179]:55118) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5J4-0003J4-RS for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:03 -0400 Received: by mail-pd0-f179.google.com with SMTP id r10so5260202pdi.24 for ; Tue, 30 Sep 2014 14:50:01 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dB0mxRx6xJJUlZxaHBOJBjEBaafUHgCwujDyoiHG/mQ=; b=c12GacaPCYFDO1AWGWROnNB60XRnS+P+y8PtNS1ACpk4g1Ow/Ddxv3+e+AL3Gmjxk6 j9DmN1bP7/tb/2ROD3wblnYjKH38Fgv0UY47+GFpTGFLoRTZ5Yh1WS37P7uoRMYcqNir WPSC8YkC6OD6dyI21ujgP/iavRguY+7mewg1DQoODLWXc4tNlhpA15yiky2bIRJfuN3a eJ6PF+rqeIdkXWqP1CMqy9WGMXNUQOFkWrsEvlyvwUpoZB26A15hBDKFNRS/KUMMU3Ua jCTEuY9z0uLIFlnD/6txLJRFmG45JT79Jo90kwr+T0dauvMFz+5Ua3MqLaUcPzocUQDw TDFA== X-Gm-Message-State: ALoCoQmq8HXQybEPUSKvV1+CQ1kRnjyWVDroYPdR93aHzSlJbImTzZrbuIr1WZvRImqZ6F8ImdrD X-Received: by 10.66.121.232 with SMTP id ln8mr7498630pab.152.1412113801689; Tue, 30 Sep 2014 14:50:01 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id qy1sm16027662pbc.27.2014.09.30.14.50.00 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 30 Sep 2014 14:50:01 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 30 Sep 2014 16:49:17 -0500 Message-Id: <1412113785-21525-6-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> References: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.179 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH v5 05/33] target-arm: make arm_current_pl() return PL3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Make arm_current_pl() return PL3 for secure PL1 and monitor mode. Increase MMU modes since mmu_index is directly infered from arm_ current_pl(). Changes assertion in arm_el_is_aa64() to allow EL3. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/cpu.h | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 101d139..c000716 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -100,7 +100,7 @@ typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info, struct arm_boot_info; -#define NB_MMU_MODES 2 +#define NB_MMU_MODES 4 /* We currently assume float and double are IEEE single and double precision respectively. @@ -753,7 +753,6 @@ static inline int arm_feature(CPUARMState *env, int feature) return (env->features & (1ULL << feature)) != 0; } - /* Return true if exception level below EL3 is in secure state */ static inline bool arm_is_secure_below_el3(CPUARMState *env) { @@ -794,11 +793,12 @@ static inline bool arm_is_secure(CPUARMState *env) /* Return true if the specified exception level is running in AArch64 state. */ static inline bool arm_el_is_aa64(CPUARMState *env, int el) { - /* We don't currently support EL2 or EL3, and this isn't valid for EL0 + /* We don't currently support EL2, and this isn't valid for EL0 * (if we're in EL0, is_a64() is what you want, and if we're not in EL0 * then the state of EL0 isn't well defined.) */ - assert(el == 1); + assert(el == 1 || el == 3); + /* AArch64-capable CPUs always run with EL1 in AArch64 mode. This * is a QEMU-imposed simplification which we may wish to change later. * If we in future support EL2 and/or EL3, then the state of lower @@ -990,9 +990,12 @@ static inline int arm_current_el(CPUARMState *env) if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) { return 0; + } else if (arm_is_secure(env)) { + /* Secure PL1 and monitor mode are mapped to PL3 */ + return 3; } - /* We don't currently implement the Virtualization or TrustZone - * extensions, so PL2 and PL3 don't exist for us. + /* We currently do not implement the Virtualization extensions, so PL2 does + * not exist for us. */ return 1; }