From patchwork Tue Sep 30 21:49:42 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 395353 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5B54B1400E0 for ; Wed, 1 Oct 2014 08:10:26 +1000 (EST) Received: from localhost ([::1]:46803 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5cm-0007Z4-Ft for incoming@patchwork.ozlabs.org; Tue, 30 Sep 2014 18:10:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43510) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5Jv-00018U-Ix for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:51:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XZ5Jp-00043P-M4 for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:55 -0400 Received: from mail-pd0-f171.google.com ([209.85.192.171]:56694) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5Jo-000421-7r for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:48 -0400 Received: by mail-pd0-f171.google.com with SMTP id ft15so4202047pdb.2 for ; Tue, 30 Sep 2014 14:50:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WxFfSvKuIOV7Gi1ncteuS7eGLB6qNOn/kGVQXXghsrc=; b=HderPUJtyJJLq662CNUDzQWUpH1ECRUEw1oTV+/PAZsMdbqSBKiUoL6xbXkaw/WJSg 5iRpHe8LZgrgWCs0iWrYV8hJJDAyqoqcouyg/HEwwAJZk0vJA1Vzr7V+Fulnh6Ue6Cbd ikeWq7w6+c4DDAFiUD1YyJoayv8RegYstPCvf9CAqtCoqKP7EI+/QOfGxhQp0QRDYxiH E33frwwftXZeZrgCU/U2+osyjL0S5v1CHJv9EKbqDoo45GnxRLOPEB26PbNZ/o2Igx4N 6OL0F5pNv86X4LVE7PzXhscg5gIsk/hCTMP+DE7XYfyjXhAgyiFvgbaIGlK82lLaEIbQ 2OXA== X-Gm-Message-State: ALoCoQlTN07rzMN1KTYvly9wQGOfWMLHODfXvRwpqvP0Fqee2ijf8F7E4oyA+0NcYV7K71YTID26 X-Received: by 10.66.164.9 with SMTP id ym9mr72942190pab.139.1412113840302; Tue, 30 Sep 2014 14:50:40 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id qy1sm16027662pbc.27.2014.09.30.14.50.39 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 30 Sep 2014 14:50:39 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 30 Sep 2014 16:49:42 -0500 Message-Id: <1412113785-21525-31-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> References: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.171 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH v5 30/33] target-arm: make MAIR0/1 banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Added CP register info entries for the ARMv7 MAIR0/1 secure banks. Signed-off-by: Greg Bellows --- target-arm/cpu.h | 1 + target-arm/helper.c | 6 ++++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 1fa9e0d..7a8eaef 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -311,6 +311,7 @@ typedef struct CPUARMState { uint32_t c9_pmuserenr; /* perf monitor user enable */ uint32_t c9_pminten; /* perf monitor interrupt enables */ uint64_t mair_el1; + uint64_t mair_el3; union { /* vector base address register */ struct { uint64_t _unused_vbar; diff --git a/target-arm/helper.c b/target-arm/helper.c index 8543813..e91a019 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -958,11 +958,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { */ { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE, .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW, - .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1), + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.mair_el3), + offsetoflow32(CPUARMState, cp15.mair_el1) }, .resetfn = arm_cp_reset_ignore }, { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE, .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW, - .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1), + .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.mair_el3), + offsetofhigh32(CPUARMState, cp15.mair_el1) }, .resetfn = arm_cp_reset_ignore }, { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,