From patchwork Sat Sep 13 16:45:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 388941 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 33C8F1400AB for ; Sun, 14 Sep 2014 02:52:59 +1000 (EST) Received: from localhost ([::1]:50951 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XSqZF-0007Eh-AD for incoming@patchwork.ozlabs.org; Sat, 13 Sep 2014 12:52:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47384) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XSqSc-0001pv-EY for qemu-devel@nongnu.org; Sat, 13 Sep 2014 12:46:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XSqSW-0000nc-F6 for qemu-devel@nongnu.org; Sat, 13 Sep 2014 12:46:06 -0400 Received: from mail-pd0-x22d.google.com ([2607:f8b0:400e:c02::22d]:52789) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XSqSW-0000nT-2s for qemu-devel@nongnu.org; Sat, 13 Sep 2014 12:46:00 -0400 Received: by mail-pd0-f173.google.com with SMTP id ft15so3455185pdb.4 for ; Sat, 13 Sep 2014 09:45:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=S/gDC+mHskliXpejkWG9etG+E6P4hY/gesP5V1jANww=; b=XKyGXTpueAb8YYebYbZUlmRYV5JSKGet8MPr6ZhXA4XerXljNMNKCEph+WojyozCx7 L1+PHIcv725OSZp233ydyob7kKRlqpYSk7zcZPkTog+Qz8ulhKa+WgwOiCpO5Fo9MppA Y2iMBneOU0fcAenvB7nomKqE2l+nkARpWVTR+jRw2MFDPL8k1mM6Pm6rt7OsDMGgvQWs 5gwiSGh4vtB+yvUz1i8TJDlzEApR+HTA1pClv93wERoa4IlUDiXLsIMpyo3cLKiu3/HB WYkNmUxVj9pbi13snKDTVxN0bCvMWl519TT/NdDtQROoZcmHxezo2GiEbMt1XN0XqKPC 99WQ== X-Received: by 10.66.240.197 with SMTP id wc5mr20322828pac.87.1410626759040; Sat, 13 Sep 2014 09:45:59 -0700 (PDT) Received: from pike.twiddle.home ([198.134.93.254]) by mx.google.com with ESMTPSA id xt10sm7240462pab.44.2014.09.13.09.45.57 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 13 Sep 2014 09:45:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 13 Sep 2014 09:45:22 -0700 Message-Id: <1410626734-3804-12-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1410626734-3804-1-git-send-email-rth@twiddle.net> References: <1410626734-3804-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c02::22d Cc: peter.maydell@linaro.org, afaerber@suse.de, aliguori@amazon.com Subject: [Qemu-devel] [PATCH 11/23] target-alpha: Use cpu_exec_interrupt qom hook X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- cpu-exec.c | 32 -------------------------------- target-alpha/cpu-qom.h | 1 + target-alpha/cpu.c | 1 + target-alpha/helper.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 46 insertions(+), 32 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index 7efcf27..2f73be4 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -597,38 +597,6 @@ int cpu_exec(CPUArchState *env) cc->do_interrupt(cpu); next_tb = 0; } -#elif defined(TARGET_ALPHA) - { - int idx = -1; - /* ??? This hard-codes the OSF/1 interrupt levels. */ - switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) { - case 0 ... 3: - if (interrupt_request & CPU_INTERRUPT_HARD) { - idx = EXCP_DEV_INTERRUPT; - } - /* FALLTHRU */ - case 4: - if (interrupt_request & CPU_INTERRUPT_TIMER) { - idx = EXCP_CLK_INTERRUPT; - } - /* FALLTHRU */ - case 5: - if (interrupt_request & CPU_INTERRUPT_SMP) { - idx = EXCP_SMP_INTERRUPT; - } - /* FALLTHRU */ - case 6: - if (interrupt_request & CPU_INTERRUPT_MCHK) { - idx = EXCP_MCHK; - } - } - if (idx >= 0) { - cpu->exception_index = idx; - env->error_code = 0; - cc->do_interrupt(cpu); - next_tb = 0; - } - } #endif /* The target hook has 3 exit conditions: False when the interrupt isn't processed, diff --git a/target-alpha/cpu-qom.h b/target-alpha/cpu-qom.h index 0caa362..b01c6c8 100644 --- a/target-alpha/cpu-qom.h +++ b/target-alpha/cpu-qom.h @@ -79,6 +79,7 @@ extern const struct VMStateDescription vmstate_alpha_cpu; #endif void alpha_cpu_do_interrupt(CPUState *cpu); +bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req); void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c index 2491f0a..a98b7d8 100644 --- a/target-alpha/cpu.c +++ b/target-alpha/cpu.c @@ -284,6 +284,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = alpha_cpu_class_by_name; cc->has_work = alpha_cpu_has_work; cc->do_interrupt = alpha_cpu_do_interrupt; + cc->cpu_exec_interrupt = alpha_cpu_exec_interrupt; cc->dump_state = alpha_cpu_dump_state; cc->set_pc = alpha_cpu_set_pc; cc->gdb_read_register = alpha_cpu_gdb_read_register; diff --git a/target-alpha/helper.c b/target-alpha/helper.c index 7c053a3..a8aa782 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -470,6 +470,50 @@ void alpha_cpu_do_interrupt(CPUState *cs) #endif /* !USER_ONLY */ } +bool alpha_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + AlphaCPU *cpu = ALPHA_CPU(cs); + CPUAlphaState *env = &cpu->env; + int idx = -1; + + /* We never take interrupts while in PALmode. */ + if (env->pal_mode) { + return false; + } + + /* Fall through the switch, collecting the highest priority + interrupt that isn't masked by the processor status IPL. */ + /* ??? This hard-codes the OSF/1 interrupt levels. */ + switch (env->ps & PS_INT_MASK) { + case 0 ... 3: + if (interrupt_request & CPU_INTERRUPT_HARD) { + idx = EXCP_DEV_INTERRUPT; + } + /* FALLTHRU */ + case 4: + if (interrupt_request & CPU_INTERRUPT_TIMER) { + idx = EXCP_CLK_INTERRUPT; + } + /* FALLTHRU */ + case 5: + if (interrupt_request & CPU_INTERRUPT_SMP) { + idx = EXCP_SMP_INTERRUPT; + } + /* FALLTHRU */ + case 6: + if (interrupt_request & CPU_INTERRUPT_MCHK) { + idx = EXCP_MCHK; + } + } + if (idx >= 0) { + cs->exception_index = idx; + env->error_code = 0; + alpha_cpu_do_interrupt(cs); + return true; + } + return false; +} + void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) {