From patchwork Sat Sep 13 04:29:21 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 388868 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3CE26140114 for ; Sat, 13 Sep 2014 14:42:19 +1000 (EST) Received: from localhost ([::1]:48421 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XSfA9-0001mw-6e for incoming@patchwork.ozlabs.org; Sat, 13 Sep 2014 00:42:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39017) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XSf5n-0001rz-FN for qemu-devel@nongnu.org; Sat, 13 Sep 2014 00:37:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XSf5f-0006dQ-LG for qemu-devel@nongnu.org; Sat, 13 Sep 2014 00:37:47 -0400 Received: from mail-qc0-x22d.google.com ([2607:f8b0:400d:c01::22d]:53152) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XSf5f-0006dJ-G6 for qemu-devel@nongnu.org; Sat, 13 Sep 2014 00:37:39 -0400 Received: by mail-qc0-f173.google.com with SMTP id i8so1545004qcq.18 for ; Fri, 12 Sep 2014 21:37:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VP65YMEh6KRABwm9da6hZ3YJLjYsIVXfS/PGA3cmvQw=; b=opymXT6K4SJ8xCkAvpUX4wH/S3G8OAsnvyJeSK0okFg8zQT2ha+1tMiJpIYiBijtdT nfgnrcJfNBlbr6+cwPmPWyfFi/xJIVS5c63g3GuZa/eCi9260QtQgX24Tm1SG9zsUtOD Oo84z4quo/fnPChHge7WXegBr500AqMylVLfA73qIPaBYkiTJynNk25lepqcYmRD7LJE 6fIgE19RQBzpkbGEUaXTUDk/sHnA54iqUhOa/zjS5PwwTKp1tDDIlBkol6NETvDE9lSF RtvPujdqVFm26/3q63wtrCBLbarZ/chDkQDfBQny6SUQT2qLPpFqz8R4IVkiKfy3iZsO GWWw== X-Received: by 10.224.156.201 with SMTP id y9mr18480010qaw.53.1410583059057; Fri, 12 Sep 2014 21:37:39 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id e5sm4575110qga.14.2014.09.12.21.37.37 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 12 Sep 2014 21:37:38 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sat, 13 Sep 2014 14:29:21 +1000 Message-Id: <1410582564-27687-8-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1410582564-27687-1-git-send-email-edgar.iglesias@gmail.com> References: <1410582564-27687-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c01::22d Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, greg.bellows@linaro.org, pbonzini@redhat.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net Subject: [Qemu-devel] [PATCH v6 07/10] target-arm: A64: Emulate the HVC insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias Reviewed-by: Greg Bellows --- target-arm/cpu.h | 1 + target-arm/helper-a64.c | 1 + target-arm/helper.c | 28 +++++++++++++++++++++++++++- target-arm/helper.h | 1 + target-arm/internals.h | 6 ++++++ target-arm/op_helper.c | 32 ++++++++++++++++++++++++++++++++ target-arm/translate-a64.c | 30 +++++++++++++++++++++--------- 7 files changed, 89 insertions(+), 10 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 7f8a410..b553f3d 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -51,6 +51,7 @@ #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ #define EXCP_STREX 10 +#define EXCP_HVC 11 /* HyperVisor Call */ #define ARMV7M_EXCP_RESET 1 #define ARMV7M_EXCP_NMI 2 diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index c6ef8e9..4e6ca26 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -476,6 +476,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs) case EXCP_BKPT: case EXCP_UDEF: case EXCP_SWI: + case EXCP_HVC: env->cp15.esr_el[new_el] = env->exception.syndrome; break; case EXCP_IRQ: diff --git a/target-arm/helper.c b/target-arm/helper.c index 4431fbb..504ff42 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3652,7 +3652,33 @@ void switch_mode(CPUARMState *env, int mode) */ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) { - return 1; + CPUARMState *env = cs->env_ptr; + unsigned int cur_el = arm_current_pl(env); + unsigned int target_el = 1; + bool route_to_el2 = false; + /* FIXME: Use actual secure state. */ + bool secure = false; + + if (!env->aarch64) { + /* TODO: Add EL2 and 3 exception handling for AArch32. */ + return 1; + } + + if (!secure + && arm_feature(env, ARM_FEATURE_EL2) + && cur_el < 2 + && (env->cp15.hcr_el2 & HCR_TGE)) { + route_to_el2 = true; + } + + target_el = MAX(cur_el, route_to_el2 ? 2 : 1); + + switch (excp_idx) { + case EXCP_HVC: + target_el = MAX(target_el, 2); + break; + } + return target_el; } static void v7m_push(CPUARMState *env, uint32_t val) diff --git a/target-arm/helper.h b/target-arm/helper.h index 1d7003b..75fc1b3 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -50,6 +50,7 @@ DEF_HELPER_2(exception_internal, void, env, i32) DEF_HELPER_3(exception_with_syndrome, void, env, i32, i32) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(wfe, void, env) +DEF_HELPER_1(pre_hvc, void, env) DEF_HELPER_3(cpsr_write, void, env, i32, i32) DEF_HELPER_1(cpsr_read, i32, env) diff --git a/target-arm/internals.h b/target-arm/internals.h index 64751a0..afcc4e0 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -53,6 +53,7 @@ static const char * const excnames[] = { [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", [EXCP_STREX] = "QEMU intercept of STREX", + [EXCP_HVC] = "Hypervisor Call", }; static inline void arm_log_exception(int idx) @@ -215,6 +216,11 @@ static inline uint32_t syn_aa64_svc(uint32_t imm16) return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); } +static inline uint32_t syn_aa64_hvc(uint32_t imm16) +{ + return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_thumb) { return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index b956216..8441c27 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -374,6 +374,38 @@ void HELPER(clear_pstate_ss)(CPUARMState *env) env->pstate &= ~PSTATE_SS; } +void HELPER(pre_hvc)(CPUARMState *env) +{ + int cur_el = arm_current_pl(env); + /* FIXME: Use actual secure state. */ + bool secure = false; + bool udef; + + /* We've already checked that EL2 exists at translation time. + * EL3.HCE has priority over EL2.HCD. + */ + if (arm_feature(env, ARM_FEATURE_EL3)) { + udef = !(env->cp15.scr_el3 & SCR_HCE); + } else { + udef = env->cp15.hcr_el2 & HCR_HCD; + } + + /* In ARMv7 and ARMv8/AArch32, HVC is udef in secure state. + * For ARMv8/AArch64, HVC is allowed in EL3. + * Note that we've already trapped HVC from EL0 at translation + * time. + */ + if (secure && (!is_a64(env) || cur_el == 1)) { + udef = true; + } + + if (udef) { + /* UDEFs trap on the HVC, roll back to the PC to the HVC insn. */ + env->exception.syndrome = syn_uncategorized(); + raise_exception(env, EXCP_UDEF); + } +} + void HELPER(exception_return)(CPUARMState *env) { int cur_el = arm_current_pl(env); diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 8e66b6c..8eaa85f 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1473,20 +1473,32 @@ static void disas_exc(DisasContext *s, uint32_t insn) switch (opc) { case 0: - /* SVC, HVC, SMC; since we don't support the Virtualization - * or TrustZone extensions these all UNDEF except SVC. - */ - if (op2_ll != 1) { - unallocated_encoding(s); - break; - } /* For SVC, HVC and SMC we advance the single-step state * machine before taking the exception. This is architecturally * mandated, to ensure that single-stepping a system call * instruction works properly. */ - gen_ss_advance(s); - gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_svc(imm16)); + switch (op2_ll) { + case 1: + gen_ss_advance(s); + gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_svc(imm16)); + break; + case 2: + if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_pl == 0) { + unallocated_encoding(s); + break; + } + /* The pre HVC helper handles cases when HVC gets trapped + * as an undefined insn by runtime configuration. */ + gen_a64_set_pc_im(s->pc - 4); + gen_helper_pre_hvc(cpu_env); + gen_ss_advance(s); + gen_exception_insn(s, 0, EXCP_HVC, syn_aa64_hvc(imm16)); + break; + default: + unallocated_encoding(s); + break; + } break; case 1: if (op2_ll != 0) {