From patchwork Thu Sep 4 17:20:36 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 385971 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id DA8C5140110 for ; Fri, 5 Sep 2014 03:48:35 +1000 (EST) Received: from localhost ([::1]:53120 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XPb97-0003BD-PC for incoming@patchwork.ozlabs.org; Thu, 04 Sep 2014 13:48:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39870) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XPaiW-0004Ok-BD for qemu-devel@nongnu.org; Thu, 04 Sep 2014 13:21:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XPaiF-0005pi-TD for qemu-devel@nongnu.org; Thu, 04 Sep 2014 13:21:04 -0400 Received: from cantor2.suse.de ([195.135.220.15]:43972 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XPaiF-0005nn-AZ; Thu, 04 Sep 2014 13:20:47 -0400 Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 531C3AD9E; Thu, 4 Sep 2014 17:20:46 +0000 (UTC) From: Alexander Graf To: qemu-ppc@nongnu.org Date: Thu, 4 Sep 2014 19:20:36 +0200 Message-Id: <1409851240-48126-49-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1409851240-48126-1-git-send-email-agraf@suse.de> References: <1409851240-48126-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x (no timestamps) [generic] X-Received-From: 195.135.220.15 Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, Tom Musta Subject: [Qemu-devel] [PULL 48/52] target-ppc: Clean up mullwo X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Tom Musta Simplify the implementation of mullwo. For 64 bit CPUs, the result is the concatenation of the upper and lower parts of the muls2_i32 operation, which may be slightly better than deposit. For 32 bit CPUs, the lower part of the muls_i32 operation is moved into the target GPR. Signed-off-by: Tom Musta Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Alexander Graf --- target-ppc/translate.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index ced295f..1062634 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -1150,19 +1150,14 @@ static void gen_mullwo(DisasContext *ctx) { TCGv_i32 t0 = tcg_temp_new_i32(); TCGv_i32 t1 = tcg_temp_new_i32(); -#if defined(TARGET_PPC64) - TCGv_i64 t2 = tcg_temp_new_i64(); -#endif tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); tcg_gen_muls2_i32(t0, t1, t0, t1); - tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); #if defined(TARGET_PPC64) - tcg_gen_ext_i32_tl(t2, t1); - tcg_gen_deposit_i64(cpu_gpr[rD(ctx->opcode)], - cpu_gpr[rD(ctx->opcode)], t2, 32, 32); - tcg_temp_free(t2); + tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); +#else + tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); #endif tcg_gen_sari_i32(t0, t0, 31);