From patchwork Mon Sep 1 11:59:54 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Koppelmann X-Patchwork-Id: 384764 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8D7361400B6 for ; Mon, 1 Sep 2014 21:00:41 +1000 (EST) Received: from localhost ([::1]:59358 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XOPLj-0003GR-Fm for incoming@patchwork.ozlabs.org; Mon, 01 Sep 2014 07:00:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34008) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XOPHT-0003PX-Oq for qemu-devel@nongnu.org; Mon, 01 Sep 2014 06:56:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XOPHO-0008WH-LK for qemu-devel@nongnu.org; Mon, 01 Sep 2014 06:56:15 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:10085) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XOPHO-0008W6-Eo for qemu-devel@nongnu.org; Mon, 01 Sep 2014 06:56:10 -0400 From: Bastian Koppelmann To: qemu-devel@nongnu.org Date: Mon, 1 Sep 2014 12:59:54 +0100 Message-Id: <1409572800-4116-10-git-send-email-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1409572800-4116-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1409572800-4116-1-git-send-email-kbastian@mail.uni-paderborn.de> X-IMT-Spam-Score: 0.0 () X-PMX-Version: 6.1.1.2430161, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2014.9.1.104820 X-IMT-Authenticated-Sender: uid=kbastian,ou=People,o=upb,c=de X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 131.234.142.9 Cc: peter.maydell@linaro.org, rth@twiddle.net Subject: [Qemu-devel] [PATCH v7 09/15] target-tricore: Add instructions of SRRS and SLRO opcode format X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add instructions of SSRS and SLRO opcode format. Add micro-op generator functions for offset loads. Signed-off-by: Bastian Koppelmann Reviewed-by: Richard Henderson --- target-tricore/translate.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index d8e23fc..258f4e4 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -107,6 +107,26 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, * Functions to generate micro-ops */ +/* Functions for load/save to/from memory */ + +static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2, + int16_t con, TCGMemOp mop) +{ + TCGv temp = tcg_temp_new(); + tcg_gen_addi_tl(temp, r2, con); + tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); + tcg_temp_free(temp); +} + +static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2, + int16_t con, TCGMemOp mop) +{ + TCGv temp = tcg_temp_new(); + tcg_gen_addi_tl(temp, r2, con); + tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); + tcg_temp_free(temp); +} + /* Functions for arithmetic instructions */ static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2) @@ -513,9 +533,17 @@ static void decode_ssr_opc(DisasContext *ctx, int op1) static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) { int op1; + int r1, r2; + int32_t const16; + TCGv temp; op1 = MASK_OP_MAJOR(ctx->opcode); + /* handle ADDSC.A opcode only being 6 bit long */ + if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) { + op1 = OPC1_16_SRRS_ADDSC_A; + } + switch (op1) { case OPC1_16_SRC_ADD: case OPC1_16_SRC_ADD_A15: @@ -568,6 +596,37 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) case OPC1_16_SSR_ST_W_POSTINC: decode_ssr_opc(ctx, op1); break; +/* SRRS-format */ + case OPC1_16_SRRS_ADDSC_A: + r2 = MASK_OP_SRRS_S2(ctx->opcode); + r1 = MASK_OP_SRRS_S1D(ctx->opcode); + const16 = MASK_OP_SRRS_N(ctx->opcode); + temp = tcg_temp_new(); + tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16); + tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp); + tcg_temp_free(temp); + break; +/* SLRO-format */ + case OPC1_16_SLRO_LD_A: + r1 = MASK_OP_SLRO_D(ctx->opcode); + const16 = MASK_OP_SLRO_OFF4(ctx->opcode); + gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); + break; + case OPC1_16_SLRO_LD_BU: + r1 = MASK_OP_SLRO_D(ctx->opcode); + const16 = MASK_OP_SLRO_OFF4(ctx->opcode); + gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); + break; + case OPC1_16_SLRO_LD_H: + r1 = MASK_OP_SLRO_D(ctx->opcode); + const16 = MASK_OP_SLRO_OFF4(ctx->opcode); + gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); + break; + case OPC1_16_SLRO_LD_W: + r1 = MASK_OP_SLRO_D(ctx->opcode); + const16 = MASK_OP_SLRO_OFF4(ctx->opcode); + gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); + break; } }