From patchwork Wed Aug 13 21:56:09 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Snow X-Patchwork-Id: 379757 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 2A22014009B for ; Thu, 14 Aug 2014 07:59:27 +1000 (EST) Received: from localhost ([::1]:50488 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XHgZp-0006a1-DF for incoming@patchwork.ozlabs.org; Wed, 13 Aug 2014 17:59:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37228) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XHgXE-00026B-Da for qemu-devel@nongnu.org; Wed, 13 Aug 2014 17:56:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XHgX6-0000Xa-Lm for qemu-devel@nongnu.org; Wed, 13 Aug 2014 17:56:44 -0400 Received: from mx1.redhat.com ([209.132.183.28]:58860) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XHgX6-0000XW-Ej for qemu-devel@nongnu.org; Wed, 13 Aug 2014 17:56:36 -0400 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id s7DLuZdG018382 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Wed, 13 Aug 2014 17:56:35 -0400 Received: from dhcp-17-12.bos.redhat.com ([10.18.17.175]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id s7DLuRRh017042; Wed, 13 Aug 2014 17:56:35 -0400 From: John Snow To: qemu-devel@nongnu.org Date: Wed, 13 Aug 2014 17:56:09 -0400 Message-Id: <1407966975-3723-3-git-send-email-jsnow@redhat.com> In-Reply-To: <1407966975-3723-1-git-send-email-jsnow@redhat.com> References: <1407966975-3723-1-git-send-email-jsnow@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: jsnow@redhat.com, armbru@redhat.com, stefanha@redhat.com, mst@redhat.com Subject: [Qemu-devel] [PATCH v3 26/32] ahci: MSI capability should be at 0x80, not 0x50. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In the Intel ICH9 data sheet, the MSI capability offset in the PCI configuration space for ICH9 AHCI devices is specified to be 0x80. Further, the PCI capability pointer should always point to 0x80 in ICH9 devices, despite the fact that AHCI 1.3 specifies that it should be pointing to PMCAP (Which in this instance would be 0x70) to maintain adherence to the Intel data sheet specifications and real observed behavior. Signed-off-by: John Snow Reviewed-by: Michael S. Tsirkin --- hw/ide/ich.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/ide/ich.c b/hw/ide/ich.c index a2f1639..d2a3ac2 100644 --- a/hw/ide/ich.c +++ b/hw/ide/ich.c @@ -71,6 +71,7 @@ #include #include +#define ICH9_MSI_CAP_OFFSET 0x80 #define ICH9_SATA_CAP_OFFSET 0xA8 #define ICH9_IDP_BAR 4 @@ -115,7 +116,6 @@ static int pci_ich9_ahci_init(PCIDevice *dev) /* XXX Software should program this register */ dev->config[0x90] = 1 << 6; /* Address Map Register - AHCI mode */ - msi_init(dev, 0x50, 1, true, false); d->ahci.irq = pci_allocate_irq(dev); pci_register_bar(dev, ICH9_IDP_BAR, PCI_BASE_ADDRESS_SPACE_IO, @@ -135,6 +135,9 @@ static int pci_ich9_ahci_init(PCIDevice *dev) (ICH9_IDP_BAR + 0x4) | (ICH9_IDP_INDEX_LOG2 << 4)); d->ahci.idp_offset = ICH9_IDP_INDEX; + /* MSI cap should be added last to be first. */ + msi_init(dev, ICH9_MSI_CAP_OFFSET, 1, true, false); + return 0; }