From patchwork Mon Aug 11 19:23:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Musta X-Patchwork-Id: 379122 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id BBB511400AB for ; Tue, 12 Aug 2014 05:26:21 +1000 (EST) Received: from localhost ([::1]:37688 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XGvEZ-00009B-QO for incoming@patchwork.ozlabs.org; Mon, 11 Aug 2014 15:26:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55688) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XGvCG-0004wG-5b for qemu-devel@nongnu.org; Mon, 11 Aug 2014 15:24:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XGvC7-0002Tv-33 for qemu-devel@nongnu.org; Mon, 11 Aug 2014 15:23:56 -0400 Received: from mail-oa0-x22c.google.com ([2607:f8b0:4003:c02::22c]:36531) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XGvC6-0002Tp-Tv; Mon, 11 Aug 2014 15:23:47 -0400 Received: by mail-oa0-f44.google.com with SMTP id eb12so6491504oac.3 for ; Mon, 11 Aug 2014 12:23:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=U55UY7Qj7zht/3Gguia2+Z57iUUBPRdIAmJcooq8pKM=; b=hi7rPfVB6N1JyYTDL3TJLEva295rC4mFefZiY/6Tl9DVRPgOtOVa1LURayCNZcc7P0 OIE9RvtYgjjX75P8CJloxiJ/2+VaoP6MD2OqrJ3IfFiazDGdoz0oIliWNGafur2TsH6g ffkTC4OEnvgvcl8PnnEdpz5JSID97E2uNv1jyYdo45IIpxccah5phIgmQWJDBLdUYLuu pP0gapMN7jxP2q4g2ezXgAJbbH0DaUlLQj1/hgNjjzDQJgR+/iCgOQBwahOAg1Q+wlo4 a3fma0d93dVK+RjhBZZeAAhxLE2std+03MH8S4rFMdmff/TVBf7Eqh+UeR04UxHok+so u7kA== X-Received: by 10.60.52.115 with SMTP id s19mr51669689oeo.21.1407785026442; Mon, 11 Aug 2014 12:23:46 -0700 (PDT) Received: from tmusta-sc.rchland.ibm.com (rchp4.rochester.ibm.com. [129.42.161.36]) by mx.google.com with ESMTPSA id u5sm1539939obt.18.2014.08.11.12.23.42 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 11 Aug 2014 12:23:45 -0700 (PDT) From: Tom Musta To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Date: Mon, 11 Aug 2014 14:23:22 -0500 Message-Id: <1407785009-6538-2-git-send-email-tommusta@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1407785009-6538-1-git-send-email-tommusta@gmail.com> References: <1407785009-6538-1-git-send-email-tommusta@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:4003:c02::22c Cc: Tom Musta , agraf@suse.de Subject: [Qemu-devel] [PATCH 1/8] target-ppc: Bug Fix: rlwinm X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The rlwinm specification includes the ROTL32 operation, which is defined to be a left rotation of two copies of the least significant 32 bits of the source GPR. The current implementation is incorrect on 64-bit implementations in that it rotates a single copy of the least significant 32 bits, padding with zeroes in the most significant bits. Fix the code to properly implement this ROTL32 operation. Signed-off-by: Tom Musta --- target-ppc/translate.c | 8 +++----- 1 files changed, 3 insertions(+), 5 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index b23933f..a27d063 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -1672,11 +1672,9 @@ static void gen_rlwinm(DisasContext *ctx) } else { TCGv t0 = tcg_temp_new(); #if defined(TARGET_PPC64) - TCGv_i32 t1 = tcg_temp_new_i32(); - tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); - tcg_gen_rotli_i32(t1, t1, sh); - tcg_gen_extu_i32_i64(t0, t1); - tcg_temp_free_i32(t1); + tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)], + cpu_gpr[rS(ctx->opcode)], 32, 32); + tcg_gen_rotli_i64(t0, t0, sh); #else tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); #endif